18071740. VARIABLE RESISTANCE MEMORY DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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VARIABLE RESISTANCE MEMORY DEVICE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Zhe Wu of Seoul (KR)

Taeguen Kim of Seoul (KR)

Jeonghee Park of Hwaseong-si (KR)

Taehyeong Kim of Seoul (KR)

Minji Yu of Seoul (KR)

VARIABLE RESISTANCE MEMORY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18071740 titled 'VARIABLE RESISTANCE MEMORY DEVICE

Simplified Explanation

The abstract describes a variable resistance memory device that includes a substrate, conductive lines, and a memory cell with specific layers. The variable resistance layer has a unique shape.

  • The patent application describes a variable resistance memory device.
  • The device includes a substrate, conductive lines, and a memory cell.
  • The memory cell has a selection element layer, an intermediate electrode layer, and a variable resistance layer.
  • The variable resistance layer has a shape of stairs with a concave center.

Potential Applications

This technology has potential applications in various fields, including:

  • Data storage devices
  • Computer memory systems
  • Electronic devices requiring non-volatile memory

Problems Solved

The technology solves several problems in memory devices, such as:

  • Limited storage capacity
  • High power consumption
  • Slow read and write speeds

Benefits

The benefits of this technology include:

  • Increased storage capacity
  • Reduced power consumption
  • Faster read and write speeds
  • Improved reliability and durability


Original Abstract Submitted

A variable resistance memory device includes a substrate, a first conductive line on the substrate, the first conductive line extending in a first horizontal direction, a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction, and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell having a selection element layer, an intermediate electrode layer, and a variable resistance layer, and the variable resistance layer having a shape of stairs with a concave center.