18065923. TWO-TRANSISTOR CHIP AND THREE-TRANSISTOR CHIP IDENTIFICATION BIT CELLS simplified abstract (International Business Machines Corporation)
Contents
TWO-TRANSISTOR CHIP AND THREE-TRANSISTOR CHIP IDENTIFICATION BIT CELLS
Organization Name
International Business Machines Corporation
Inventor(s)
Kangguo Cheng of Schenectady NY (US)
Julien Frougier of Albany NY (US)
Ruilong Xie of Niskayuna NY (US)
Chanro Park of Clifton Park NY (US)
Min Gyu Sung of Latham NY (US)
TWO-TRANSISTOR CHIP AND THREE-TRANSISTOR CHIP IDENTIFICATION BIT CELLS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18065923 titled 'TWO-TRANSISTOR CHIP AND THREE-TRANSISTOR CHIP IDENTIFICATION BIT CELLS
The patent application describes a method for programming an array of bit cells to generate a unique identification code for a semiconductor structure using random gate dielectric failures.
- Utilizes random gate dielectric failures at transistors to create a binary identification code.
- Gate dielectric fails source-side for a first logic state and drain-side for a second logic state.
- Failure of gate dielectric is influenced by its thinness compared to a control gate dielectric's thickness.
- Failure is initiated by applying voltage to both thin and thick gate dielectrics.
- Bit cells can consist of two or three transistors, such as field effect transistors.
Potential Applications: - Semiconductor manufacturing - Security and authentication systems - Anti-counterfeiting measures
Problems Solved: - Generating unique identification codes - Enhancing security measures in semiconductor devices
Benefits: - Increased security through unique identification codes - Improved reliability in authentication systems
Commercial Applications: Title: "Semiconductor Security Systems Using Random Gate Dielectric Failures" This technology can be utilized in the development of secure semiconductor devices for various industries, including electronics, automotive, and healthcare.
Questions about the technology: 1. How does the random gate dielectric failure method enhance security in semiconductor structures?
- The random gate dielectric failures create unique identification codes, increasing security measures.
2. What are the potential drawbacks of using gate dielectric failures for generating identification codes?
- The method may require additional testing and quality control measures to ensure reliability.
Original Abstract Submitted
Methods and structure are provided for programming an array of bit cells to create a unique identification code for a semiconductor structure. Random failure of a gate dielectric at a transistor is utilized to generate a binary identification code. A portion of the gate is located above a source and a portion is located above a drain, a first logic state can be applied where the gate dielectric fails source-side and a second logic state can be applied where the gate dielectric fails drain-side. The gate dielectric preferentially fails as a function of its thinness versus the thickness of a second gate dielectric of a second transistor which acts as a control for failure of the gate dielectric. Failure is initiated based upon a voltage applied to both the thin gate dielectric and the thick dielectric. A bit cell can include two or three transistors, e.g., field effect transistors.
