18064260. PREVENTING SOURCE/DRAIN EPI MERGE WITHOUT CELL SIZE INCREASE simplified abstract (International Business Machines Corporation)
Contents
PREVENTING SOURCE/DRAIN EPI MERGE WITHOUT CELL SIZE INCREASE
Organization Name
International Business Machines Corporation
Inventor(s)
Min Gyu Sung of Latham NY (US)
Julien Frougier of Albany NY (US)
Ruilong Xie of Niskayuna NY (US)
Chanro Park of Clifton Park NY (US)
PREVENTING SOURCE/DRAIN EPI MERGE WITHOUT CELL SIZE INCREASE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18064260 titled 'PREVENTING SOURCE/DRAIN EPI MERGE WITHOUT CELL SIZE INCREASE
Simplified Explanation:
The patent application describes a semiconductor device with two nanosheet field effect transistors (FETs) on a substrate, each with a different gate stack height.
- The semiconductor device includes a first nanosheet FET with a gate stack on the substrate.
- A second nanosheet FET is placed adjacent to the first one on the substrate.
- The second FET has a different gate stack height compared to the first FET.
Key Features and Innovation:
- Utilization of nanosheet FET technology.
- Different gate stack heights for improved performance.
- Enhanced functionality and efficiency in semiconductor devices.
Potential Applications:
This technology can be applied in:
- Integrated circuits.
- Microprocessors.
- Memory devices.
Problems Solved:
- Improved transistor performance.
- Enhanced device efficiency.
- Better control over semiconductor operations.
Benefits:
- Increased speed and performance.
- Reduced power consumption.
- Enhanced overall device functionality.
Commercial Applications:
Potential commercial uses include:
- Consumer electronics.
- Telecommunications.
- Automotive industry.
Prior Art:
Further research can be conducted in the field of nanosheet FET technology and semiconductor device design to explore existing patents and innovations.
Frequently Updated Research:
Stay updated on advancements in nanosheet FET technology and semiconductor device manufacturing processes for potential improvements and new applications.
Questions about Semiconductor Device with Nanosheet FETs:
1. What are the specific advantages of using nanosheet FETs in semiconductor devices? 2. How does the different gate stack height in the second FET contribute to overall device performance?
Original Abstract Submitted
A semiconductor device includes a first nanosheet field effect transistor (PET) having a first gate stack arranged on a substrate. A second nanosheet FET is arranged on the substrate adjacent to the first nanosheet FET. The second FET includes a second gate stack, wherein a top of the first gate stack and a top of the second gate stack have different heights.
