18059937. MULTIPLE-CORE MEMORY CONTROLLER simplified abstract (QUALCOMM Incorporated)
Contents
- 1 MULTIPLE-CORE MEMORY CONTROLLER
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 MULTIPLE-CORE MEMORY CONTROLLER - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Unanswered Questions
- 1.11 Original Abstract Submitted
MULTIPLE-CORE MEMORY CONTROLLER
Organization Name
Inventor(s)
Pankaj Deshmukh of San Diego CA (US)
Shyamkumar Thoziyoor of San Diego CA (US)
Vishakh Balakuntalam Visweswara of Vancouver (CA)
Jungwon Suh of San Diego CA (US)
Subbarao Palacharla of San Diego CA (US)
MULTIPLE-CORE MEMORY CONTROLLER - A simplified explanation of the abstract
This abstract first appeared for US patent application 18059937 titled 'MULTIPLE-CORE MEMORY CONTROLLER
Simplified Explanation
The patent application describes memory systems that can operate portions of a memory core at a lower frequency than the memory clock to reduce power consumption and cost.
- Memory controller with two cores for scheduling memory operations in different portions of the clock cycle.
- Support for operating memory core at a frequency lower than the memory clock.
- Aim to reduce power consumption and cost in memory systems.
Potential Applications
This technology could be applied in:
- Mobile devices
- IoT devices
- Embedded systems
Problems Solved
- High power consumption in memory systems
- High costs associated with memory operations
Benefits
- Reduced power consumption
- Lower costs for memory operations
- Improved efficiency in memory systems
Potential Commercial Applications
Optimizing Memory Systems for Power Efficiency
Possible Prior Art
No known prior art.
Unanswered Questions
1. How does this technology impact the overall performance of memory systems? 2. Are there any potential drawbacks or limitations to operating memory cores at a lower frequency?
Original Abstract Submitted
This disclosure provides systems, methods, and devices for memory systems that support operating a least portions of a memory core at a frequency lower than a memory clock to reduce power consumption and cost. In a first aspect, a memory controller includes a first core for scheduling a first memory operation for a first portion of a clock cycle of the memory clock and includes a second core for scheduling a second memory operation for a second portion of the clock cycle of the memory clock. Other aspects and features are also claimed and described.
