18059856. AUXILIARY ENGINE FOR HARDWARE VIRTUALIZATION simplified abstract (QUALCOMM Incorporated)

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AUXILIARY ENGINE FOR HARDWARE VIRTUALIZATION

Organization Name

QUALCOMM Incorporated

Inventor(s)

Abhijeet Dey of Bengaluru (IN)

Animesh Behera of Bengaluru (IN)

Joby Abraham of Bangalore (IN)

Amrit Anand Amresh of Bangalore (IN)

AUXILIARY ENGINE FOR HARDWARE VIRTUALIZATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 18059856 titled 'AUXILIARY ENGINE FOR HARDWARE VIRTUALIZATION

Simplified Explanation

The abstract describes a patent application for processing data using symmetrical processing engines and an auxiliary processing engine. The process involves receiving input data, processing it using the auxiliary processing engine, further processing the data in the symmetrical processing engine, and outputting the processed data.

  • Symmetrical processing engines coupled to an auxiliary processing engine
  • Input data received and processed by the auxiliary processing engine
  • Output data transmitted to the auxiliary processing engine
  • Further processing of data in the symmetrical processing engine
  • Processed data outputted after further processing

Potential Applications

This technology could be applied in various industries such as telecommunications, data processing, and computer systems.

Problems Solved

This technology helps in efficiently processing large amounts of data by utilizing multiple processing engines in a symmetrical configuration.

Benefits

- Increased processing speed and efficiency - Scalability for handling large datasets - Improved data processing capabilities

Potential Commercial Applications

"Optimizing Data Processing with Symmetrical and Auxiliary Engines"

Possible Prior Art

There may be prior art related to parallel processing systems or data processing techniques that involve multiple processing engines working together.

What are the specific technical specifications of the symmetrical processing engines mentioned in the abstract?

The abstract does not provide specific technical specifications of the symmetrical processing engines, such as the number of cores, clock speed, or memory capacity.

How does the auxiliary processing engine communicate with the symmetrical processing engines in the described process?

The abstract does not detail the communication protocol or mechanism used for the auxiliary processing engine to interact with the symmetrical processing engines during the data processing process.


Original Abstract Submitted

Techniques are described herein for processing data. For instance, a process can include receiving input data by a symmetrical processing engine of two or more symmetrical processing engines coupled to an auxiliary processing engine. The process can further include receiving an indication to process the input data using a module of the auxiliary processing engine, transmitting output data to the auxiliary processing engine, receiving processed data from the auxiliary processing engine, further processing the processed data in one or more portions of a pipeline of modules of the symmetrical processing engine, and outputting the further processed data.