18059076. PROVIDING MEMORY REGION PREFETCHING IN PROCESSOR-BASED DEVICES simplified abstract (QUALCOMM Incorporated)

PROVIDING MEMORY REGION PREFETCHING IN PROCESSOR-BASED DEVICES

Organization Name

QUALCOMM Incorporated

Inventor(s)

Suryanarayana Murthy Durbhakula of Hyderabad (IN)

PROVIDING MEMORY REGION PREFETCHING IN PROCESSOR-BASED DEVICES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18059076 titled 'PROVIDING MEMORY REGION PREFETCHING IN PROCESSOR-BASED DEVICES

Simplified Explanation

The abstract describes a patent application for a region prefetcher circuit in processor-based devices that improves memory access efficiency by prefetching memory blocks based on access bitmaps.

• The region prefetcher circuit includes multiple access bitmaps corresponding to contiguous memory regions, with each bitmap containing bits for memory blocks.
• When a memory access request is detected, the circuit sets the corresponding bit in the access bitmap to indicate the request.
• Upon detecting a prefetch trigger event, the circuit identifies unset bits in the access bitmap and prefetches memory blocks corresponding to those unset bits.

Potential Applications

The technology can be applied in various processor-based devices such as computers, servers, and mobile devices to enhance memory access performance.

Problems Solved

1. Improves memory access efficiency by prefetching memory blocks based on access patterns. 2. Reduces latency in memory access by proactively fetching data before it is requested.

Benefits

1. Enhanced overall system performance by reducing memory access latency. 2. Optimized memory utilization by prefetching data based on access patterns. 3. Improved user experience with faster response times for memory-intensive applications.

Potential Commercial Applications

Optimizing memory access in high-performance computing systems, data centers, and mobile devices can lead to improved efficiency and user satisfaction.

Possible Prior Art

One possible prior art could be the use of cache memory to prefetch data based on access patterns to reduce memory access latency. Another could be the use of predictive algorithms to anticipate memory access requests and prefetch data accordingly.

How does the region prefetcher circuit handle memory access requests to non-contiguous memory regions?

The abstract does not provide information on how the circuit deals with memory access requests that span multiple non-contiguous memory regions.

What impact does the region prefetcher circuit have on power consumption in processor-based devices?

The abstract does not address the potential effects of the region prefetcher circuit on power consumption in devices where energy efficiency is critical.

Original Abstract Submitted

Providing memory region prefetching in processor-based devices is disclosed. In some aspects, a processor-based device comprises a region prefetcher circuit that comprises a plurality of access bitmaps corresponding to a plurality of contiguous memory regions of a system memory device. Each access bitmap comprises a plurality of bits corresponding to a plurality of memory blocks of a contiguous memory region. The region prefetcher circuit detects a memory access request to a memory block of a contiguous memory region, identifies an access bitmap corresponding to the contiguous memory region, and identifies a bit corresponding to the memory block. The region prefetcher circuit sets the bit to indicate the memory access request to the memory block. The region prefetcher circuit subsequently detects a prefetch trigger event, and, in response, identifies one or more unset bits of the access bitmap, and prefetches one or more memory blocks corresponding to the unset bits.