18056158. PHYSICALLY UNCLONABLE CELL USING DUAL-INTERLOCKING AND ERROR CORRECTION TECHNIQUES simplified abstract (NVIDIA Corporation)

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PHYSICALLY UNCLONABLE CELL USING DUAL-INTERLOCKING AND ERROR CORRECTION TECHNIQUES

Organization Name

NVIDIA Corporation

Inventor(s)

Mahmut Ersin Sinangil of Los Altos CA (US)

Sudhir Shrikantha Kudva of Dublin CA (US)

Nikola Nedovic of San Jose CA (US)

Carl Thomas Gray of Apex NC (US)

PHYSICALLY UNCLONABLE CELL USING DUAL-INTERLOCKING AND ERROR CORRECTION TECHNIQUES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18056158 titled 'PHYSICALLY UNCLONABLE CELL USING DUAL-INTERLOCKING AND ERROR CORRECTION TECHNIQUES

Simplified Explanation

The patent application describes PUF cells utilizing a dual-interlocking scheme to improve noise immunity and stability across different V/T conditions and uses over time in noisy environments. The PUF cells can be used in conjunction with error detection techniques to screen out unstable cells and generate a device-specific bit pattern, such as a master key.

  • Dual-interlocking scheme for PUF cells
  • Improved noise immunity and stability
  • Utilization with error detection techniques
  • Generation of device-specific bit patterns

Potential Applications

The technology can be applied in secure communication systems, authentication processes, and cryptographic key generation.

Problems Solved

The technology addresses issues related to noise interference, stability, and security in PUF cells used for generating device-specific bit patterns.

Benefits

The benefits of this technology include enhanced security, improved reliability, and increased resistance to noise interference.

Potential Commercial Applications

Potential commercial applications include secure data storage systems, IoT devices, and secure communication networks.

Possible Prior Art

Prior art may include existing PUF cell technologies with single-interlocking schemes or without error detection techniques.

Unanswered Questions

1. How does the dual-interlocking scheme in PUF cells improve noise immunity compared to traditional single-interlocking schemes? 2. What specific error detection techniques are recommended for use with PUF cells to screen out unstable cells?


Original Abstract Submitted

PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.