18055566. ADJUSTING MEMORY POWER CONSUMPTION simplified abstract (Microsoft Technology Licensing, LLC)
Contents
- 1 ADJUSTING MEMORY POWER CONSUMPTION
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 ADJUSTING MEMORY POWER CONSUMPTION - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
ADJUSTING MEMORY POWER CONSUMPTION
Organization Name
Microsoft Technology Licensing, LLC
Inventor(s)
Gilad Kirshenboim of Petach Tiqva (IL)
ADJUSTING MEMORY POWER CONSUMPTION - A simplified explanation of the abstract
This abstract first appeared for US patent application 18055566 titled 'ADJUSTING MEMORY POWER CONSUMPTION
Simplified Explanation
The memory system described in the patent application monitors the bit error rate in data read from a memory and adjusts its operation to decrease power consumption while maintaining an acceptable memory error condition.
- The memory system monitors the bit error rate in data read from the memory.
- It determines if the monitored bit error rate satisfies an acceptable memory error condition.
- If the error rate is acceptable, the memory system adjusts its operation to decrease power consumption.
- The adjusted operation results in a new bit error rate that still satisfies the acceptable memory error condition.
Potential Applications
The technology could be applied in various memory systems, such as computer RAM, to optimize power consumption while ensuring data integrity.
Problems Solved
This technology addresses the issue of balancing power consumption and data integrity in memory systems, ensuring efficient operation without compromising reliability.
Benefits
The benefits of this technology include improved energy efficiency in memory systems, extended device battery life, and enhanced overall system performance.
Potential Commercial Applications
Potential commercial applications of this technology include mobile devices, servers, data centers, and any other systems that rely on memory for data storage and processing.
Possible Prior Art
One possible prior art could be memory systems that monitor bit error rates but do not dynamically adjust operation based on error conditions to optimize power consumption.
=== What are the specific methods used to monitor the bit error rate in the memory system? The specific methods used to monitor the bit error rate in the memory system are not detailed in the abstract. Further information on the monitoring techniques employed would provide a clearer understanding of the technology.
=== How does the memory system adjust its operation to decrease power consumption while maintaining an acceptable memory error condition? The abstract mentions that the memory system adjusts its operation to decrease power consumption, but it does not specify the exact mechanisms or strategies used for this adjustment. More information on the specific techniques employed would be beneficial to understand the innovation better.
Original Abstract Submitted
A memory system may monitor a bit error rate in data read from a memory in the memory system. The memory system may determine that the monitored bit error rate satisfies an acceptable memory error condition. The memory system may adjust operation of the memory system to decrease the power consumption of the memory system, wherein the adjusted operation results in a new bit error rate monitored from data read from the memory that satisfies the acceptable memory error condition.
