18055047. DUAL PORT DUAL POWER RAIL MEMORY ARCHITECTURE simplified abstract (NVIDIA Corporation)
Contents
- 1 DUAL PORT DUAL POWER RAIL MEMORY ARCHITECTURE
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 DUAL PORT DUAL POWER RAIL MEMORY ARCHITECTURE - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
DUAL PORT DUAL POWER RAIL MEMORY ARCHITECTURE
Organization Name
Inventor(s)
Lalit Gupta of FREMONT CA (US)
Jason Golbus of Palo Alto CA (US)
Jesse San-Jey Wang of Santa Clara CA (US)
DUAL PORT DUAL POWER RAIL MEMORY ARCHITECTURE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18055047 titled 'DUAL PORT DUAL POWER RAIL MEMORY ARCHITECTURE
Simplified Explanation
The patent application describes multi-ported memories with write peripheral logic operating in one voltage domain and read peripheral logic operating in another voltage domain, with voltage domain crossings localized in the bit cells of the memory array.
- The write peripheral logic and read peripheral logic are on opposite sides of the bit cell array.
- Voltage domain crossings are localized in the bit cells of the memory array.
Potential Applications
This technology could be applied in:
- High-speed data processing systems
- Embedded systems requiring efficient memory access
Problems Solved
This technology addresses:
- Voltage domain crossing issues in multi-ported memories
- Efficient operation of write and read peripheral logic in different voltage domains
Benefits
The benefits of this technology include:
- Improved memory access speed
- Reduced power consumption
- Enhanced reliability of memory operations
Potential Commercial Applications
"Optimized Multi-Ported Memories for High-Speed Data Processing Systems"
Possible Prior Art
No prior art information is available at this time.
Unanswered Questions
How does this technology impact overall system performance?
This technology can significantly improve system performance by enhancing memory access speed and reducing power consumption.
What are the potential cost implications of implementing this technology?
The cost implications of implementing this technology may include initial investment in new memory architectures and potential savings in power consumption over time.
Original Abstract Submitted
Multi-ported memories that include write peripheral logic configured to operate in a first voltage domain, read peripheral logic configured to operate in a second voltage domain, and at least one bit cell array, wherein the write peripheral logic and the read peripheral logic are disposed on opposite sides of the bit cell array and voltage domain crossings between the first voltage domain and the second voltage domain are localized in bit cells of the at least one bit cell array.
