18054986. MEMORY DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
MEMORY DEVICE
Organization Name
Inventor(s)
Kyunghwan Lee of Suwon-si (KR)
MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18054986 titled 'MEMORY DEVICE
Simplified Explanation
The abstract describes a memory device that includes a substrate, a fin structure, a gate structure, and source/drain regions. The gate structure consists of a trap layer, a blocking layer, and a gate electrode layer. The first source/drain region is doped with or contains dopants of a first conductivity type, while the second source/drain region is doped with or contains dopants of a second conductivity type that is different from the first.
- The memory device includes a fin structure on a substrate.
- A gate structure is formed on the fin structure, consisting of a trap layer, a blocking layer, and a gate electrode layer.
- The first source/drain region is located at one end of the fin structure and is doped with or contains dopants of a first conductivity type.
- The second source/drain region is located at the other end of the fin structure and is doped with or contains dopants of a second conductivity type that is different from the first.
Potential applications of this technology:
- Memory devices in electronic devices such as smartphones, tablets, and computers.
- Storage devices in data centers and servers.
- Embedded memory in integrated circuits for various applications.
Problems solved by this technology:
- Provides a memory device with improved performance and reliability.
- Enables efficient data storage and retrieval.
- Allows for higher density memory devices.
Benefits of this technology:
- Enhanced memory device performance.
- Increased data storage capacity.
- Improved reliability and durability.
- Enables faster data access and processing.
Original Abstract Submitted
A memory device is provided. The memory device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a first source/drain at one end of the fin structure, and a second source/drain at the other end of the fin structure, wherein the gate structure includes a trap layer, a blocking layer, and a gate electrode layer sequentially stacked on the fin structure, the first source/drain is doped with or has incorporated therein dopants of a first conductivity-type, and the second source/drain is doped with or has incorporated therein dopants of a second conductivity-type dopants that are different from the dopants of the first conductivity-type.
