18054376. Multi-stage Thread Scheduling simplified abstract (Apple Inc.)

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Multi-stage Thread Scheduling

Organization Name

Apple Inc.

Inventor(s)

Benjiman L. Goodman of Cedar Park TX (US)

Anjana Rajendran of Austin TX (US)

Sheenam Jayaswal of Austin TX (US)

Terence M. Potter of Austin TX (US)

Yoong Chert Foo of London (GB)

Multi-stage Thread Scheduling - A simplified explanation of the abstract

This abstract first appeared for US patent application 18054376 titled 'Multi-stage Thread Scheduling

Simplified Explanation

The patent application describes techniques for multi-stage thread scheduling in processor circuitry with multiple channel pipelines and execution pipelines.

  • Processor circuitry includes multiple channel pipelines and multiple execution pipelines shared by the channel pipelines.
  • First scheduler circuitry assigns threads to channels.
  • Second scheduler circuitry assigns operations from channels to execution pipelines.
  • Execution pipelines provide backpressure information to adjust thread priorities.
  • Techniques aim to reduce channel conflicts and resource starvation.

Potential Applications

The technology described in the patent application could be applied in:

  • High-performance computing systems
  • Data centers
  • Real-time processing applications

Problems Solved

The technology addresses the following issues:

  • Channel conflicts in multi-threaded systems
  • Starvation of execution resources
  • Efficient thread scheduling in complex processor architectures

Benefits

The benefits of this technology include:

  • Improved system performance
  • Enhanced resource utilization
  • Reduced contention for execution resources

Potential Commercial Applications

A potential commercial application for this technology could be in:

  • Server processors
  • Networking equipment
  • Embedded systems

Possible Prior Art

One possible prior art in this field could be:

  • Previous techniques for thread scheduling in multi-core processors

Unanswered Questions

How does the technology handle priority inversion among threads?

The patent application does not specifically address how priority inversion is handled in the multi-stage thread scheduling process.

What impact does this technology have on power consumption in processor systems?

The patent application does not discuss the potential impact of this technology on power consumption in processor systems.


Original Abstract Submitted

Techniques are disclosed relating to multi-stage thread scheduling. In some embodiments, processor circuitry includes multiple channel pipelines for multiple channels and multiple execution pipelines shared by the channel pipelines and configured to perform different types of operations provided by the channel pipelines. First scheduler circuitry may arbitrate among threads to assign threads to channels. Second scheduler circuitry may arbitrate among channels to assign an operation from a given channel to a given execution pipeline. The execution pipelines may provide backpressure information to the first scheduler circuitry based on execution status and the first scheduler circuitry may adjust priority of a thread for assignment to a channel based on the backpressure information. Disclosed techniques may reduce channel conflicts and starvation for execution resources.