18054249. HOST PERFORMANCE BOOSTER L2P HANDOFF simplified abstract (QUALCOMM Incorporated)
Contents
- 1 HOST PERFORMANCE BOOSTER L2P HANDOFF
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 HOST PERFORMANCE BOOSTER L2P HANDOFF - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
HOST PERFORMANCE BOOSTER L2P HANDOFF
Organization Name
Inventor(s)
Madhu Yashwanth Boenapalli of Hyderabad (IN)
Surendra Paravada of Hyderabad (IN)
Sai Praneeth Sreeram of Anantapur (IN)
HOST PERFORMANCE BOOSTER L2P HANDOFF - A simplified explanation of the abstract
This abstract first appeared for US patent application 18054249 titled 'HOST PERFORMANCE BOOSTER L2P HANDOFF
Simplified Explanation
The patent application describes methods for synchronizing logical-to-physical (L2P) tables before entering a hibernate mode on a computing device. Here are some key points to explain the innovation:
- The host controller of the computing device determines if the L2P tables in DRAM and SRAM are out of synchronization.
- If the tables are out of sync, the host controller retrieves modified L2P map entries from the SRAM before the UFS device enters hibernate mode.
- The host controller updates the L2P table in DRAM with the modified entries to ensure synchronization before entering hibernate mode.
Potential Applications
This technology can be applied in various computing devices that use flash storage, such as smartphones, tablets, and laptops.
Problems Solved
1. Ensures data integrity and consistency between L2P tables before entering hibernate mode. 2. Prevents data loss or corruption that may occur due to unsynchronized tables.
Benefits
1. Improved reliability and performance of computing devices. 2. Enhanced data protection and security. 3. Seamless transition to hibernate mode without data loss.
Potential Commercial Applications
The technology can be utilized in the development of next-generation storage devices and systems for consumer electronics, enterprise servers, and data centers.
Possible Prior Art
There may be prior art related to methods for synchronizing data tables in computing devices before entering low-power modes, but specific examples are not provided in the patent application.
Unanswered Questions
How does this technology impact power consumption in computing devices?
The patent application does not address how the synchronization of L2P tables before entering hibernate mode affects power consumption. This information would be valuable for understanding the overall efficiency of the technology.
Are there any limitations to the synchronization process described in the patent application?
The patent application does not mention any potential limitations or challenges that may arise during the synchronization of L2P tables. Identifying and addressing these limitations could provide a more comprehensive understanding of the technology's practical implementation.
Original Abstract Submitted
Methods that may be performed by a host controller of a computing device for synchronizing logical-to-physical (L2P) tables before entering a hibernate mode are disclosed. Embodiment methods may include determining whether a first L2P table stored in a dynamic random-access memory (DRAM) communicatively connected to the host controller is out of synchronization with a second L2P table stored in a static random-access memory (SRAM) of a universal flash storage (UFS) device communicatively connected to the host controller via a link. If the first and second L2P tables are out of synch, the host controller may retrieve at least one modified L2P map entry from the second L2P table when the UFS device is configured to enter a hibernate mode from the UFS device, and update the first L2P tabled with the at least one modified L2P map entry before the link and the UFS device enter the hibernate mode.
