18052689. SEMICONDUCTOR MEMORY DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR MEMORY DEVICE
Organization Name
Inventor(s)
Kiseok Lee of Hwaseong-si (KR)
Moonyoung Jeong of Suwon-si (KR)
Han-Sik Yoo of Seongnam-si (KR)
Hyungeun Choi of Suwon-si (KR)
SEMICONDUCTOR MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18052689 titled 'SEMICONDUCTOR MEMORY DEVICE
Simplified Explanation
The patent application describes a semiconductor memory device that consists of a cell array structure and a peripheral circuit structure. The cell array structure includes bonding pads connected to memory cells, while the peripheral circuit structure includes bonding pads connected to peripheral circuits.
- The cell array structure is composed of stacked horizontal conductive patterns and vertical conductive patterns that intersect the stack vertically.
- A power capacitor is integrated into a planarization insulating layer that covers part of the stack.
- The second bonding pads in the peripheral circuit structure are bonded to the first bonding pads in the cell array structure.
Potential applications of this technology:
- Memory devices in various electronic devices such as smartphones, tablets, and computers.
- Data storage in cloud computing centers and data centers.
Problems solved by this technology:
- Efficient integration of memory cells and peripheral circuits in a semiconductor memory device.
- Improved power management and stability in memory operations.
Benefits of this technology:
- Enhanced performance and reliability of semiconductor memory devices.
- Increased memory capacity and data transfer speed.
- Reduced power consumption and improved energy efficiency.
Original Abstract Submitted
A semiconductor memory device may include a cell array structure including first bonding pads, which are electrically connected to memory cells, and a peripheral circuit structure including second bonding pads, which are electrically connected to peripheral circuits and are bonded to the first bonding pads. The cell array structure may include a stack including horizontal conductive patterns stacked in a vertical direction, a vertical structure including vertical conductive patterns , which are provided to cross the stack in the vertical direction, and a power capacitor provided in a planarization insulating layer covering a portion of the stack.
