18047950. APPARATUSES, SYSTEMS, AND METHODS FOR DATA TIMING ALIGNMENT WITH FAST ALIGNMENT MODE simplified abstract (Micron Technology, Inc.)
Contents
APPARATUSES, SYSTEMS, AND METHODS FOR DATA TIMING ALIGNMENT WITH FAST ALIGNMENT MODE
Organization Name
Inventor(s)
BAOKANG Wang of Sagamihara (JP)
TAKUYA Miyagi of Sagamihara (JP)
APPARATUSES, SYSTEMS, AND METHODS FOR DATA TIMING ALIGNMENT WITH FAST ALIGNMENT MODE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18047950 titled 'APPARATUSES, SYSTEMS, AND METHODS FOR DATA TIMING ALIGNMENT WITH FAST ALIGNMENT MODE
Abstract: Apparatuses, systems, and methods for data timing alignment with fast alignment mode. A stacked memory device includes an interface die and a number of core die. The interface and the core die each have an adjustable delay circuit adjusted by an interface delay code or a respective core delay code. The delay codes are adjusted based on a measured phase difference along a replica path. In a default maintenance state, the delay codes may be adjusted based on an average of the phase differences over time. Each time the phase difference matches a previous phase difference, the interface die changes a count value associated with that core die. If one or more of the count values cross a threshold, a state machine of the interface die enters a different delay adjustment state where averaging is not used. This may allow for correction of systemic errors such as voltage drift.
Key Features and Innovation:
- Stacked memory device with interface and core die having adjustable delay circuits.
- Delay codes adjusted based on measured phase differences along a replica path.
- Default maintenance state adjusts delay codes based on average phase differences over time.
- State machine enters different delay adjustment state when count values associated with core die cross a threshold.
- Allows for correction of systemic errors like voltage drift.
Potential Applications: - Memory devices - Data processing systems - Communication systems
Problems Solved: - Addressing phase misalignment in stacked memory devices - Correcting systemic errors such as voltage drift
Benefits: - Improved data timing alignment - Enhanced performance of memory devices - Increased reliability in data processing systems
Commercial Applications: Title: "Advanced Data Timing Alignment Technology for Memory Devices" This technology can be utilized in: - Semiconductor industry for memory devices - Telecommunication sector for communication systems - Data centers for improved data processing efficiency
Prior Art: No prior art information available at this time.
Frequently Updated Research: There is ongoing research in the field of memory devices and data processing systems to enhance data timing alignment and address systemic errors like voltage drift.
Questions about Data Timing Alignment Technology: 1. How does this technology improve the performance of memory devices? 2. What are the potential challenges in implementing this fast alignment mode in stacked memory devices?
Original Abstract Submitted
Apparatuses, systems, and methods for data timing alignment with fast alignment mode. A stacked memory device includes an interface die and a number of core die. The interface and the core die each have an adjustable delay circuit adjusted by an interface delay code or a respective core delay code. The delay codes are adjusted based on a measured phase difference along a replica path. In a default maintenance state, the delay codes may be adjusted based on an average of the phase differences over time. Each time the phase difference matches a previous phase difference, the interface die changes a count value associated with that core die. If one or more of the count values cross a threshold, a state machine of the interface die enters a different delay adjustment state where averaging is not used. This may allow for correction of systemic errors such as voltage drift.
