17985498. CLOCKED COMPARATOR WITH SERIES DECISION FEEDBACK EQUALIZATION simplified abstract (QUALCOMM Incorporated)

From WikiPatents
Jump to navigation Jump to search

CLOCKED COMPARATOR WITH SERIES DECISION FEEDBACK EQUALIZATION

Organization Name

QUALCOMM Incorporated

Inventor(s)

Patrick Isakanian of El Dorado Hills CA (US)

Darius Valaee of San Diego CA (US)

CLOCKED COMPARATOR WITH SERIES DECISION FEEDBACK EQUALIZATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17985498 titled 'CLOCKED COMPARATOR WITH SERIES DECISION FEEDBACK EQUALIZATION

Simplified Explanation

The abstract describes an input stage of a comparator circuit, which includes multiple transistors and feedback signals for decision-making.

  • The input stage of the comparator includes a first transistor connected to a first input, a second transistor connected to a second input, a third transistor in series with the first transistor, and a fourth transistor in series with the second transistor.
  • Additionally, a fifth transistor receives a first decision feedback signal and is connected to the gate of the third transistor, while a sixth transistor receives a second decision feedback signal and is connected to the gate of the fourth transistor.

Potential Applications

This technology can be applied in high-speed analog-to-digital converters, voltage comparators, and other precision measurement systems.

Problems Solved

This innovation helps improve the accuracy and speed of decision-making in comparator circuits, leading to more reliable performance in various electronic devices.

Benefits

The input stage design enhances the overall efficiency and precision of comparator circuits, contributing to better signal processing and data conversion in electronic systems.

Potential Commercial Applications

  • "Enhancing Comparator Circuits for Improved Performance in Electronic Devices"

Possible Prior Art

There may be prior art related to comparator circuit designs using feedback signals for decision-making, but specific examples are not provided in the abstract.

Unanswered Questions

How does this technology compare to existing comparator circuit designs in terms of speed and accuracy?

This article does not provide a direct comparison with existing designs, so it is unclear how this technology specifically improves speed and accuracy.

What are the potential limitations or challenges in implementing this input stage design in practical electronic systems?

The abstract does not address any potential challenges or limitations that may arise when implementing this input stage design in real-world applications.


Original Abstract Submitted

An input stage of a comparator includes a first transistor, wherein a gate of the first transistor is coupled to a first input of the input stage, a second transistor, wherein a gate of the second transistor is coupled to a second input of the input stage, a third transistor coupled in series with the first transistor, and a fourth transistor coupled in series with the second transistor. The input stage also includes a fifth transistor, wherein a gate of the fifth transistor is configured to receive a first decision feedback signal, and a drain of the fifth transistor is coupled to a gate of the third transistor. The input stage further includes a sixth transistor, wherein a gate of the sixth transistor is configured to receive a second decision feedback signal, and a drain of the sixth transistor is coupled to a gate of the fourth transistor.