17973234. NAMED AND CLUSTER BARRIERS simplified abstract (Intel Corporation)
Contents
- 1 NAMED AND CLUSTER BARRIERS
NAMED AND CLUSTER BARRIERS
Organization Name
Inventor(s)
Chunhui Mei of San Diego CA (US)
John A. Wiegert of Aloha OR (US)
Yongsheng Liu of San Diego CA (US)
Ben J. Ashbaugh of Folsom CA (US)
NAMED AND CLUSTER BARRIERS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17973234 titled 'NAMED AND CLUSTER BARRIERS
Simplified Explanation
Embodiments described herein provide a technique to facilitate the synchronization of workgroups executed on multiple graphics cores of a graphics core cluster. One embodiment provides a graphics core including a cache memory and a graphics core coupled with the cache memory. The graphics core includes execution resources to execute an instruction via a plurality of hardware threads and barrier circuitry to synchronize execution of the plurality of hardware threads, wherein the barrier circuitry is configured to provide a plurality of re-usable named barriers.
- Graphics core cluster synchronization technique:
- Facilitates synchronization of workgroups on multiple graphics cores - Graphics core includes cache memory and execution resources - Barrier circuitry for synchronizing hardware threads - Provides re-usable named barriers for synchronization
Potential Applications
This technology could be applied in: - High-performance computing - Graphics processing units (GPUs) - Virtual reality systems - Artificial intelligence applications
Problems Solved
- Efficient synchronization of workgroups on multiple graphics cores - Improved performance in parallel processing tasks - Enhanced coordination of hardware threads
Benefits
- Increased efficiency in graphics processing - Faster execution of parallel tasks - Improved overall system performance
Potential Commercial Applications
Optimized for: - Gaming industry - Data centers - Scientific research institutions - Automotive industry
Possible Prior Art
One possible prior art in this field is the use of barrier synchronization techniques in parallel computing systems to manage the execution of multiple threads efficiently.
What are the specific hardware requirements for implementing this synchronization technique?
The specific hardware requirements for implementing this synchronization technique include a graphics core with cache memory, execution resources, and barrier circuitry capable of managing named barriers for synchronization.
How does this technique compare to existing methods of synchronization in graphics core clusters?
This technique offers a more efficient and flexible way to synchronize workgroups on multiple graphics cores compared to traditional methods. By providing re-usable named barriers, it allows for better coordination and management of hardware threads, leading to improved overall system performance.
Original Abstract Submitted
Embodiments described herein provide a technique to facilitate the synchronization of workgroups executed on multiple graphics cores of a graphics core cluster. One embodiment provides a graphics core including a cache memory and a graphics core coupled with the cache memory. The graphics core includes execution resources to execute an instruction via a plurality of hardware threads and barrier circuitry to synchronize execution of the plurality of hardware threads, wherein the barrier circuitry is configured to provide a plurality of re-usable named barriers.
