17957847. GALVANIC ISOLATION DEVICE simplified abstract (TEXAS INSTRUMENTS INCORPORATED)

GALVANIC ISOLATION DEVICE

Organization Name

TEXAS INSTRUMENTS INCORPORATED

Inventor(s)

Jeffrey Alan West of Plano TX (US)

Sreeram N. S. of Bangalore (IN)

Kashyap Barot of Bangalore (IN)

Thomas Dyer Bonifield of Dallas TX (US)

Byron Lovell Williams of Plano TX (US)

Elizabeth Costner Stewart of Dallas TX (US)

GALVANIC ISOLATION DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17957847 titled 'GALVANIC ISOLATION DEVICE

Simplified Explanation

The microelectronic device described in the patent application includes a galvanic isolation device on a silicon substrate and a semiconductor device on a semiconductor substrate. The galvanic isolation device consists of a lower isolation element, an upper isolation element, and a dielectric plateau made of inorganic dielectric material. The semiconductor device includes an active component and device bond pads.

• Lower isolation element and upper isolation element separated by a dielectric plateau
• Lower bond pads connected to the lower isolation element
• Upper bond pads connected to the upper isolation element
• Device bond pads coupled to the active component
• First electrical connections to the lower bond pads and second electrical connections to the upper bond pads

Potential Applications

The technology described in this patent application could be used in:

• Power electronics
• Communication systems
• Industrial control systems

Problems Solved

This technology helps in:

• Providing galvanic isolation in microelectronic devices
• Enhancing the reliability and performance of semiconductor devices

Benefits

The benefits of this technology include:

• Improved safety by preventing electrical interference
• Increased efficiency in electronic systems
• Enhanced durability of microelectronic devices

Potential Commercial Applications

The potential commercial applications of this technology could be in:

• Automotive industry
• Aerospace sector
• Telecommunications market

Possible Prior Art

One possible prior art for this technology could be the use of traditional galvanic isolation techniques in microelectronic devices.

What are the manufacturing processes involved in creating this microelectronic device?

The manufacturing processes involved in creating this microelectronic device include:

• Silicon substrate preparation
• Deposition of inorganic dielectric material
• Bond pad connection
• Semiconductor device integration

How does the galvanic isolation device improve the performance of the semiconductor device?

The galvanic isolation device improves the performance of the semiconductor device by:

• Preventing electrical interference
• Enhancing signal integrity
• Increasing overall reliability

Original Abstract Submitted

A microelectronic device includes a galvanic isolation device on a silicon substrate and a semiconductor device on a semiconductor substrate. The galvanic isolation device includes a lower isolation element over the silicon substrate and an upper isolation element above the lower isolation element, separated by a dielectric plateau that comprises inorganic dielectric material extending from the lower isolation element to the upper isolation element. The galvanic isolation device includes lower bond pads connected to the lower isolation element adjacent to the dielectric plateau, and upper bond pads over the dielectric plateau, connected to the upper isolation element. The semiconductor device includes an active component, and device bond pads coupled to the active component. The microelectronic device includes first electrical connections to the lower bond pads and second electrical connections to the upper bond pads. The first electrical connections or the second electrical connections are connected to the device bond pads.