17931937. CACHING LOOKUP TABLES FOR BLOCK FAMILY ERROR AVOIDANCE simplified abstract (Micron Technology, Inc.)
CACHING LOOKUP TABLES FOR BLOCK FAMILY ERROR AVOIDANCE
Organization Name
Inventor(s)
Shakeel Isamohiuddin Bukhari of San Jose CA (US)
CACHING LOOKUP TABLES FOR BLOCK FAMILY ERROR AVOIDANCE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17931937 titled 'CACHING LOOKUP TABLES FOR BLOCK FAMILY ERROR AVOIDANCE
Simplified Explanation
- A memory device caches a subset of block family error avoidance (BFEA) lookup tables associated with host data in a first memory location. - The block family is based on a time window or temperature window during which the host data was written. - The memory device receives a read command associated with host data and determines a threshold voltage offset based on the block family and the subset of BFEA tables. - The memory device computes a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data. - The memory device reads the host data from the first memory location using the modified threshold voltage.
Potential Applications
- Data storage devices - Solid-state drives - Memory systems
Problems Solved
- Error avoidance in memory devices - Efficient data retrieval - Improved data integrity
Benefits
- Enhanced data reliability - Improved performance in memory devices - Reduced risk of data corruption
Original Abstract Submitted
In some implementations, a memory device may cache a subset of one or more block family error avoidance (BFEA) lookup tables associated with a block family associated with host data in a first memory location. The block family may be based on at least one of a time window during which the host data was written or a temperature window at which the host data was written. The memory device may receive a read command associated with host data and determine, based on the block family and the subset of the one or more BFEA tables, a threshold voltage offset associated with the host data. The memory device may compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data. The memory device may read, using the modified threshold voltage, the host data from the first memory location.
