17915421. DUMMY PIXEL CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE simplified abstract (BOE TECHNOLOGY GROUP CO., LTD.)
Contents
DUMMY PIXEL CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE
Organization Name
BOE TECHNOLOGY GROUP CO., LTD.
Inventor(s)
DUMMY PIXEL CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17915421 titled 'DUMMY PIXEL CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE
The present disclosure pertains to a dummy pixel circuit, a display panel, and a display device in the field of display technology. The dummy pixel circuit is positioned between two through vias in a display panel and consists of a pixel sub-circuit and a dummy sub-circuit.
- The pixel sub-circuit includes one or more first transistors with the control electrode of the first transistor connected to the first gate line.
- The dummy sub-circuit comprises one or more second transistors, with the control electrode of the dummy sub-circuit connected to the first gate line.
- The second transistor consumes power from the first gate line, increasing the total load of the pixel circuit and enhancing the luminance of the corresponding pixel, reducing display mura.
Potential Applications: - This technology can be applied in various display devices such as televisions, monitors, and smartphones. - It can improve the overall display quality by reducing display mura and enhancing luminance.
Problems Solved: - Addresses the issue of display mura in display panels. - Enhances the luminance of pixels, improving overall display quality.
Benefits: - Improved display quality with reduced mura. - Enhanced luminance for better visual experience.
Commercial Applications: - This technology can be utilized in the manufacturing of high-quality display panels for consumer electronics, leading to better viewing experiences for users.
Questions about the Technology: 1. How does the dummy pixel circuit contribute to reducing display mura? 2. What are the specific benefits of increasing the total load of the pixel circuit in terms of display quality?
Original Abstract Submitted
The present disclosure relates to a dummy pixel circuit, a display panel, and a display device, which belongs to the field of display. The dummy pixel circuit is applicable to a display panel provided with two through vias and disposed between the two through vias, and the dummy pixel circuit includes a pixel sub-circuit and a dummy sub-circuit. The pixel sub-circuit includes one or more first transistors, wherein a control electrode of the first transistor is electrically connected to the first gate line. The dummy sub-circuit includes one or more second transistors, wherein a control electrode of the dummy sub-circuit is electrically connected to the first gate line, a first electrode of the second transistor is electrically connected to a first electrode of a corresponding one of the one or more first transistors, and a second electrode of the second transistor is electrically connected to a second electrode of the corresponding first transistor. Each of the one or more first transistors corresponds to at least one of the one or more second transistors. The second transistor consumes the power transmitted transferred by the first gate line, and thus a total load of the pixel circuit electrically connected to the first gate line is increased. In this way, the pixel, to which the pixel circuit electrically connected to the first gate line corresponds, has an increased luminance, thereby mitigating display mura of display panel.
