17900075. PARALLEL PIPE LATCH FOR MEMORY ACCESS OPERATIONS simplified abstract (Micron Technology, Inc.)

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PARALLEL PIPE LATCH FOR MEMORY ACCESS OPERATIONS

Organization Name

Micron Technology, Inc.

Inventor(s)

Jaeil Kim of Boise ID (US)

PARALLEL PIPE LATCH FOR MEMORY ACCESS OPERATIONS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17900075 titled 'PARALLEL PIPE LATCH FOR MEMORY ACCESS OPERATIONS

Simplified Explanation

The memory device described in the patent application includes memory and control circuitry, as well as pipelatch circuitry and error correction code (ECC) circuitry. The control circuitry can receive a command to access the memory, and then provide command data of the command to the pipelatch circuitry and ECC circuitry. The pipelatch circuitry is responsible for receiving and maintaining the command data for a period longer than the error calculation time of the ECC circuitry.

  • Memory device with memory and control circuitry
  • Control circuitry receives commands to access memory
  • Command data is provided to pipelatch circuitry and ECC circuitry
  • Pipelatch circuitry maintains command data for a longer period than ECC error calculation time

Potential Applications

  • Data storage devices
  • Computer memory systems
  • Embedded systems

Problems Solved

  • Ensures accurate data retrieval and storage
  • Reduces errors in memory access
  • Improves overall system reliability

Benefits

  • Enhanced data integrity
  • Improved system performance
  • Increased reliability in memory operations


Original Abstract Submitted

A memory device comprises memory and control circuitry. The control circuitry can receive a command to access the memory. Responsive to receiving the command to access the memory, the control circuitry can provide command data of the command to pipelatch circuitry and error correction code (ECC) circuitry. The memory device further includes pipelatch circuitry to receive command data of the command from the control circuitry and maintain the command data for a period of time of a duration longer than error calculation time of the ECC circuitry.