17899859. MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY simplified abstract (Micron Technology, Inc.)
MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY
Organization Name
Inventor(s)
John D. Porter of Boise ID (US)
MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY - A simplified explanation of the abstract
This abstract first appeared for US patent application 17899859 titled 'MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY
Simplified Explanation
- Systems and methods for sensing an accessed voltage value associated with a memory cell are described. - Memory arrays may include a different number of sense amplifiers. - Each sense amplifier may include capacitors with different capacitance values to compensate for differences in received charges associated with similar memory states caused by various circuit delays. - Sense amplifiers may include capacitors with varying capacitance values to compensate for delayed activation caused by delayed provision of charges associated with targeted memory states.
Potential Applications
- Memory storage devices - Computer systems - Electronic devices
Problems Solved
- Compensating for differences in received charges associated with memory states - Addressing delayed activation caused by circuit delays
Benefits
- Improved accuracy in sensing voltage values associated with memory cells - Enhanced performance in memory arrays with varying circuit delays - Increased reliability in memory storage devices
Original Abstract Submitted
Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense amplifiers. Moreover, each sense amplifier may include capacitors with different capacitance values to compensate for a difference in received charges associated with a similar memory state caused by various circuit delays. For example, farther memory cells from a word line driver may receive activation signals with higher delays which in turn may result in delayed activation. As such, the sense amplifiers may include capacitors with varying capacitance values to compensate for an amount charge received at a latching time caused by delayed provision of charges associated with the targeted memory states.
