17899849. MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY simplified abstract (Micron Technology, Inc.)
Contents
MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY
Organization Name
Inventor(s)
John D. Porter of Boise ID (US)
MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY - A simplified explanation of the abstract
This abstract first appeared for US patent application 17899849 titled 'MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY
Simplified Explanation
The patent application describes systems and methods for sensing an accessed voltage value associated with a memory cell.
- Memory array may include a different number of sense components.
- Each sense component may receive latching signals to latch the accessed voltage value of memory cells based on different timings.
- Memory array may latch digit line voltages of memory cells positioned farther from a word line driver at a later time based on a latching signal with a higher delay.
- Circuitry is included to receive and/or generate delayed latching signals.
- Selection circuitry is included for latching the digit line voltages based on selected delayed latching signals.
Potential applications of this technology:
- Memory devices
- Data storage systems
- Embedded systems
Problems solved by this technology:
- Efficient sensing of voltage values in memory cells
- Improved performance in memory arrays
Benefits of this technology:
- Higher accuracy in reading accessed voltage values
- Increased reliability in memory operations
- Enhanced speed and efficiency in memory array operations
Original Abstract Submitted
Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense components. Moreover, each sense component may receive latching signals to latch the accessed voltage value of memory cells of the memory array based on different timings. For example, the memory array may latch digit line voltages of memory cells positioned farther from a respective word line driver at a later time based on a latching signal with a higher delay. Such memory arrays may include circuitry to receive and/or generate the delayed latching signals as well as selection circuitry for latching the digit line voltages based on a selected delayed latching signals.
