17898333. MEMORY BLOCK ERASE PROTOCOL simplified abstract (Micron Technology, Inc.)
Contents
MEMORY BLOCK ERASE PROTOCOL
Organization Name
Inventor(s)
Chun Sum Yeung of San Jose CA (US)
Ting Luo of Santa Clara CA (US)
Guang Hu of Mountain View CA (US)
Jonathan S. Parry of Boise ID (US)
MEMORY BLOCK ERASE PROTOCOL - A simplified explanation of the abstract
This abstract first appeared for US patent application 17898333 titled 'MEMORY BLOCK ERASE PROTOCOL
Simplified Explanation
- A memory block erase protocol is described in the patent application. - The system includes a memory device with a memory array and a processing device. - The processing device determines a metric value associated with the memory array. - If the metric value is below a predetermined threshold, the processing device initiates an erase protocol. - The processing device erases sets of memory cells associated with memory blocks in the memory array. - The processing device can receive programming commands and perform programming operations on memory cells.
Potential Applications
- Data storage devices - Solid-state drives - Flash memory devices
Problems Solved
- Efficient memory management - Preventing data corruption - Extending the lifespan of memory devices
Benefits
- Improved performance of memory devices - Enhanced reliability of data storage - Increased longevity of memory cells
Original Abstract Submitted
Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a metric associated with the memory array. Responsive to determine that the value of the metric is below a predetermined threshold, the processing device is further to initiate an erase protocol of the memory device. The processing device is further to erase sets of memory cells associated with one or more memory blocks of the memory array. The processing device is further to receive a programming command directed to the first set of memory cells. The processing device is further to perform a programming operation with respect to a set of memory cells responsive to receiving the programming command.
