17897957. MEMORY DEVICE CLOCK MAPPING simplified abstract (Micron Technology, Inc.)
Contents
MEMORY DEVICE CLOCK MAPPING
Organization Name
Inventor(s)
Kallol Mazumder of Dallas TX (US)
Navya Sri Sreeram of McKinney TX (US)
Scott E. Smith of Plano TX (US)
MEMORY DEVICE CLOCK MAPPING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17897957 titled 'MEMORY DEVICE CLOCK MAPPING
Simplified Explanation
The abstract describes a memory apparatus with clock circuitry that generates first and second clock signals based on a system clock signal, with the signals being out of phase. Detection circuitry determines if an initial operation coincides with a rising edge of the first or second clock signal. Processing circuitry provides odd and even clock signals based on the first and second clock signals and the detection result, with the signals being in or out of phase depending on the detection result.
- Memory apparatus with clock circuitry
- Generates first and second clock signals based on system clock signal
- Signals are out of phase
- Detection circuitry determines coincidence with rising edge of clock signals
- Processing circuitry provides odd and even clock signals based on detection result
- Signals can be in or out of phase based on detection result
Potential Applications
- Memory systems - Data storage devices - Computer hardware
Problems Solved
- Efficient memory operation - Synchronization of clock signals - Improved performance of memory devices
Benefits
- Enhanced memory functionality - Increased data processing speed - Improved system reliability
Original Abstract Submitted
An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The apparatus can include processing circuitry to provide an odd clock signal and an even clock signal based first and second clock signals and the detection result. The processing circuitry can provide the odd clock signal and the even clock signal out of phase or in phase with the first clock signal and the second clock signal depending on the detection result.
