17897913. PARKING THREADS IN BARREL PROCESSOR FOR MANAGING CACHE EVICTION REQUESTS simplified abstract (Micron Technology, Inc.)
PARKING THREADS IN BARREL PROCESSOR FOR MANAGING CACHE EVICTION REQUESTS
Organization Name
Inventor(s)
Christopher Baronne of Allen TX (US)
PARKING THREADS IN BARREL PROCESSOR FOR MANAGING CACHE EVICTION REQUESTS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17897913 titled 'PARKING THREADS IN BARREL PROCESSOR FOR MANAGING CACHE EVICTION REQUESTS
Simplified Explanation
The abstract describes devices and techniques for parking threads in a barrel processor to manage cache eviction requests. The barrel processor includes eviction circuitry and is able to detect threads with memory access operations, determine when a data cache line needs to be evicted, copy the thread into a park queue, evict the data cache line, identify empty cycles in the memory request pipeline, schedule the thread to execute during the empty cycle, and remove the thread from the park queue.
- Detect threads with memory access operations
- Determine when a data cache line needs to be evicted
- Copy the thread into a park queue
- Evict the data cache line
- Identify empty cycles in the memory request pipeline
- Schedule the thread to execute during the empty cycle
- Remove the thread from the park queue
Potential Applications
- Improving cache management in processors
- Enhancing memory access efficiency
Problems Solved
- Efficient cache eviction handling
- Optimized memory access operations
Benefits
- Increased performance in memory access
- Better utilization of cache resources
- Enhanced overall processor efficiency
Original Abstract Submitted
Devices and techniques for parking threads in a barrel processor for managing cache eviction requests are described herein. A barrel processor includes eviction circuitry and is configured to perform operations to: (a) detect a thread that includes a memory access operation, the thread entering a memory request pipeline of the barrel processor; (b) determine that a data cache line has to be evicted from a data cache for the thread to perform the memory access operation; (c) copy the thread into a park queue; (d) evict a data cache line from the data cache; (e) identify an empty cycle in the memory request pipeline; (f) schedule the thread to execute during the empty cycle; and (g) remove the thread from the park queue.
