17897399. Memory Circuitry And Method Used In Forming Memory Circuitry simplified abstract (Micron Technology, Inc.)

Memory Circuitry And Method Used In Forming Memory Circuitry

Organization Name

Micron Technology, Inc.

Inventor(s)

John D. Hopkins of Meridian ID (US)

Alyssa N. Scarbrough of Boise ID (US)

Memory Circuitry And Method Used In Forming Memory Circuitry - A simplified explanation of the abstract

This abstract first appeared for US patent application 17897399 titled 'Memory Circuitry And Method Used In Forming Memory Circuitry

Simplified Explanation

The memory circuitry described in the patent application comprises a unique design of memory cells arranged in strings within a stack structure.

• The memory cells are arranged in strings that extend through alternating insulative tiers and conductive tiers within the stack.
• The stack extends from a memory-array region into a stair-step region, with a flight of stairs along one direction and multiple different-depth treads along the orthogonal direction.
• The treads in the stairs are made of conducting material from the conductive tiers, with a pattern of higher-depth and lower-depth treads in lateral succession.

Potential Applications:

• This memory circuitry design could be used in various electronic devices requiring high-density memory storage, such as smartphones, tablets, and computers.
• It could also be applied in data centers and servers for efficient data storage and retrieval.

Problems Solved:

• This design allows for a more compact and efficient memory circuitry layout, optimizing space utilization within electronic devices.
• The unique stair-step structure provides a novel way to increase memory capacity without significantly increasing the physical footprint.

Benefits:

• Increased memory capacity within a smaller physical space, leading to more efficient and powerful electronic devices.
• Improved data storage and retrieval speeds due to the optimized layout of memory cells within the stack structure.

Original Abstract Submitted

Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a flight of stairs extending along a first direction. Multiple different-depth treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The multiple different-depth treads in the individual stairs comprise in lateral-succession along the second direction a first higher-depth tread, a lower-depth tread, and a second higher-depth tread. Methods are also disclosed.