17896523. SEMICONDUCTOR DEVICES simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR DEVICES
Organization Name
Inventor(s)
Jinyoung Choi of Hwaseong-si (KR)
SEMICONDUCTOR DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17896523 titled 'SEMICONDUCTOR DEVICES
Simplified Explanation
The patent application describes a semiconductor device with a specific structure and configuration.
- The device includes a substrate with an active region and an element isolation layer adjacent to it.
- A gate electrode is placed on the substrate, crossing the active region in a perpendicular direction.
- Multiple channel layers are positioned on the active region, separated from each other along a vertical direction, and surrounded by the gate electrode.
- A source/drain region is located in a recess of the active region next to the gate electrode and connected to the channel layers.
- The gate electrode has different lengths on the active region and the element isolation layer, with the length on the isolation layer being greater.
Potential applications of this technology:
- Integrated circuits
- Microprocessors
- Memory devices
- Power devices
Problems solved by this technology:
- Improved performance and efficiency of semiconductor devices
- Enhanced control over the flow of current
- Reduction of leakage current
Benefits of this technology:
- Higher speed and performance of electronic devices
- Lower power consumption
- Increased reliability and stability of semiconductor devices
Original Abstract Submitted
A semiconductor device is provided. The semiconductor device includes: a substrate with an active region extending in a first direction; an element isolation layer, adjacent to the active region, in the substrate; a gate electrode on the substrate and extending in a second direction which crosses the first direction; a plurality of channel layers on the active region, spaced apart from each other along a third direction perpendicular to an upper surface of the substrate, and surrounded by the gate electrode; and a source/drain region provided in a recess of the active region adjacent to the gate electrode, and connected to the plurality of channel layers. In the first direction, the gate electrode has a first length on the active region and a second length, greater than the first length, on the element isolation layer.
