17895393. METHOD AND SYSTEM FOR LOW NOISE SUB-SAMPLING PHASE LOCK LOOP (PLL) ARCHITECTURE WITH AUTOMATIC DYNAMIC FREQUENCY ACQUISITION simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
- 1 METHOD AND SYSTEM FOR LOW NOISE SUB-SAMPLING PHASE LOCK LOOP (PLL) ARCHITECTURE WITH AUTOMATIC DYNAMIC FREQUENCY ACQUISITION
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 METHOD AND SYSTEM FOR LOW NOISE SUB-SAMPLING PHASE LOCK LOOP (PLL) ARCHITECTURE WITH AUTOMATIC DYNAMIC FREQUENCY ACQUISITION - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Original Abstract Submitted
METHOD AND SYSTEM FOR LOW NOISE SUB-SAMPLING PHASE LOCK LOOP (PLL) ARCHITECTURE WITH AUTOMATIC DYNAMIC FREQUENCY ACQUISITION
Organization Name
Inventor(s)
SUSHRANT Monga of BENGALURU (IN)
VISHNU Kalyanamahadevi Gopalan Jawarlal of BENGALURU (IN)
METHOD AND SYSTEM FOR LOW NOISE SUB-SAMPLING PHASE LOCK LOOP (PLL) ARCHITECTURE WITH AUTOMATIC DYNAMIC FREQUENCY ACQUISITION - A simplified explanation of the abstract
This abstract first appeared for US patent application 17895393 titled 'METHOD AND SYSTEM FOR LOW NOISE SUB-SAMPLING PHASE LOCK LOOP (PLL) ARCHITECTURE WITH AUTOMATIC DYNAMIC FREQUENCY ACQUISITION
Simplified Explanation
The abstract describes a sub-sampling phase lock loop, which is a system used to synchronize the phase and frequency of a clock signal with a reference signal. The system includes samplers that sample the clock signal phases at the sampling edges of the reference signal phases. A phase detector selects a phase for a particular instant of the reference signal based on sampled values that meet a predetermined criteria. The phase detector tracks the selected phase at every successive instant of the reference signal and determines a sampled value associated with the selected phase. A processing unit acquires frequency information based on the tracking of the selected phase.
- The patent describes a sub-sampling phase lock loop system.
- The system uses samplers to obtain sampled values of clock signal phases.
- The clock signal is generated by a voltage controlled oscillator.
- The sampling is done at the sampling edges of the reference signal phases.
- The reference signal is generated by a reference clock generator.
- A phase detector selects a phase for a particular instant of the reference signal.
- The selection is based on at least one sampled value satisfying a predetermined criteria.
- The phase detector tracks the selected phase at every successive instant of the reference signal.
- The phase detector also determines a sampled value associated with the selected phase.
- A processing unit acquires frequency information based on the tracking of the selected phase.
Potential Applications
- Synchronization of clock signals with reference signals in various electronic systems.
- Frequency acquisition and tracking in communication systems.
- Phase and frequency synchronization in data transmission and reception.
Problems Solved
- Ensures accurate synchronization of clock signals with reference signals.
- Provides a reliable method for acquiring and tracking frequency information.
- Reduces phase and frequency errors in electronic systems.
Benefits
- Improved performance and reliability of electronic systems.
- Enhanced accuracy in frequency acquisition and tracking.
- Reduced phase and frequency errors, leading to better data transmission and reception.
Original Abstract Submitted
A sub-sampling phase lock loop includes samplers that obtain sampled values by sampling clock signal phases corresponding to a clock signal generated by a voltage controlled oscillator at sampling edges of reference signal phases of a reference signal generated by a reference clock generator over a reference clock cycle; and a phase detector that selects a phase for a particular instant of the reference signal based on at least one sampled value satisfying a predetermined criteria, the phase corresponding to a clock signal phase value and a reference signal phase value respectively selected from the clock signal and reference signal phases, the phase detector tracks the selected phase at every successive instant of the reference signal, and determines a sampled value associated with the selected phase in every successive instant of the reference signal; and a processing unit that acquires frequency information based on the tracking of the selected phase.
