17895053. CONFIGURABLE DATA PROTECTION CIRCUITRY FOR MEMORY DEVICES simplified abstract (Micron Technology, Inc.)
Contents
CONFIGURABLE DATA PROTECTION CIRCUITRY FOR MEMORY DEVICES
Organization Name
Inventor(s)
Marco Sforzin of Cernusco Sul Naviglio (IT)
CONFIGURABLE DATA PROTECTION CIRCUITRY FOR MEMORY DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17895053 titled 'CONFIGURABLE DATA PROTECTION CIRCUITRY FOR MEMORY DEVICES
Simplified Explanation
The patent application describes configurable data protection circuitry for memory systems, allowing for different codeword configurations and operating modes based on the number of memory devices and input/output width.
- Memory includes multiple memory devices and a memory controller connected via multiple channels.
- Channels consist of subsets of memory devices.
- Memory controller has data protection circuitry to support different codeword configurations and operating modes.
- Can switch between different operating modes based on the number of memory devices and input/output width.
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- Potential Applications
- Data storage systems
- Cloud computing infrastructure
- High-performance computing
- Problems Solved
- Efficient data protection in memory systems with varying configurations
- Flexibility to adapt to different operating modes based on system requirements
- Benefits
- Improved data reliability and integrity
- Enhanced performance and scalability
- Cost-effective memory management options
Original Abstract Submitted
Systems, apparatus, and methods related to configurable data protection circuitry. A memory includes a plurality of memory devices and a memory controller that can be coupled to the memory via a plurality of channels. The channels comprise respective subsets of the plurality of memory devices. The memory controller comprises data protection circuitry to accommodate a first codeword configuration of a number of codewords responsive to the plurality of memory devices having a first operating mode corresponding to a first input/output (I/O) width and accommodate a second codeword configuration of the number of codewords responsive to the plurality of memory devices having a second operating mode corresponding to a second I/O width, as well as switch between the first operating mode of the plurality of memory devices and the second operating mode of the plurality of memory devices.
