17889053. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Jongho Lee of Hwaseong-si (KR)
Cheolsoo Han of Hwaseong-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17889053 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The patent application describes a semiconductor package that includes a substrate with substrate pads, a semiconductor chip with conductive chip pads, and bonding wires connecting the substrate pads to the chip pads. The bonding wires consist of two types: first and second bonding wires.
- The substrate has two regions: a first region between the chip pads and substrate pads, and a second region between the first region and substrate pads.
- The second bonding wire reaches its maximum vertical level on the first region of the substrate.
- On the first region, the first bonding wire is positioned at a higher level than the second bonding wire.
- On the second region, the second bonding wire is positioned at a higher level than the first bonding wire.
Potential applications of this technology:
- Semiconductor packaging industry
- Electronics manufacturing
Problems solved by this technology:
- Efficient and reliable connection between the semiconductor chip and the substrate
- Proper positioning and arrangement of bonding wires
Benefits of this technology:
- Improved performance and functionality of semiconductor packages
- Enhanced reliability and durability of electronic devices
- Simplified manufacturing process for semiconductor packages
Original Abstract Submitted
A semiconductor package comprising a substrate including substrate pads on a top surface thereof, a first upper semiconductor chip on the substrate and including conductive chip pads, and bonding wires coupled to the substrate pads and the first upper semiconductor chip. The bonding wires include first and second bonding wires. The substrate has a first region between the conductive chip pads and the substrate pads, and a second region between the first region and the substrate pads. The second bonding wire has a maximum vertical level on the first region of the substrate. On the first region of the substrate, the first bonding wire is at a level higher than that of the second bonding wire. On the second region of the substrate, the second bonding wire is at a level higher than that of the first bonding wire.
