17888467. SUPPORT STRUCTURE FOR MULTIPLE, ALTERNATING EPITAXIAL SILICON simplified abstract (Micron Technology, Inc.)
SUPPORT STRUCTURE FOR MULTIPLE, ALTERNATING EPITAXIAL SILICON
Organization Name
Inventor(s)
Scott E. Sills of Boise ID (US)
David K. Hwang of Boise ID (US)
Yoshitaka Nakamura of Boise ID (US)
Glen H. Walters of Boise ID (US)
SUPPORT STRUCTURE FOR MULTIPLE, ALTERNATING EPITAXIAL SILICON - A simplified explanation of the abstract
This abstract first appeared for US patent application 17888467 titled 'SUPPORT STRUCTURE FOR MULTIPLE, ALTERNATING EPITAXIAL SILICON
Simplified Explanation
The patent application describes a system for vertically stacked memory cells with horizontally oriented access devices and storage nodes. The access devices have two source/drain regions separated by single crystalline silicon channel regions. A support structure is provided for the single crystalline silicon. Access lines connect to gates surrounding the channel regions, forming gate all around (GAA) structures. The memory cells have storage nodes connected to one source/drain region and vertical digit lines connected to the other source/drain region.
- The patent application describes a system for vertically stacked memory cells.
- The access devices in the system have horizontally oriented structures.
- The access devices have two source/drain regions separated by single crystalline silicon channel regions.
- A support structure is provided for the single crystalline silicon.
- Access lines connect to gates surrounding the channel regions, forming gate all around (GAA) structures.
- The memory cells in the system have storage nodes connected to one source/drain region.
- The memory cells also have vertical digit lines connected to the other source/drain region.
Potential Applications
This technology could be applied in various memory storage devices, such as:
- Solid-state drives (SSDs)
- Random-access memory (RAM)
- Flash memory
Problems Solved
The technology addresses the following problems:
- Efficiently stacking memory cells in a vertical arrangement
- Providing horizontally oriented access devices for improved performance
- Ensuring single crystalline silicon channel regions for better conductivity
Benefits
The technology offers the following benefits:
- Increased memory storage capacity due to vertical stacking
- Improved performance with horizontally oriented access devices
- Enhanced conductivity with single crystalline silicon channel regions
Original Abstract Submitted
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. A support structure is provided to the epitaxially grown, single crystalline Si. Horizontally oriented access lines connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from the channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.
