17888299. DYNAMIC PARITY SCHEME simplified abstract (Micron Technology, Inc.)
Contents
DYNAMIC PARITY SCHEME
Organization Name
Inventor(s)
Gennaro Schettino of Casamicciola Terme (NA) (IT)
Luca Porzio of Casalnuovo (NA) (IT)
DYNAMIC PARITY SCHEME - A simplified explanation of the abstract
This abstract first appeared for US patent application 17888299 titled 'DYNAMIC PARITY SCHEME
Simplified Explanation
- Memory system with dynamic parity scheme - Memory device with blocks of memory cells storing data and parity information - Quantity of pages storing parity information can be increased to improve reliability - Increase in quantity of pages can be triggered by threshold access operations or errors detected - Aim to enhance data reliability in memory systems
Potential Applications
- Data storage systems - Computer memory systems - Cloud storage services
Problems Solved
- Data corruption in memory systems - Improving data reliability - Enhancing error detection and correction capabilities
Benefits
- Increased data reliability - Improved error detection and correction - Enhanced performance of memory systems
Original Abstract Submitted
Methods, systems, and devices for a dynamic parity scheme are described. A memory system may include a memory device with multiple blocks of memory cells, where each block includes a first quantity of pages of memory cells storing data and a second quantity of pages of memory cells storing parity information associated with the data. In some cases, the memory system may increase the quantity of pages in a block of memory cells storing parity information to improve a reliability of the data stored in the block of memory cells. For example, the memory system may increase the quantity of pages storing parity information at the block of memory cells after performing a threshold quantity of access operations at the block of memory cells or in response to detecting more than a threshold quantity of errors in data stored at the block of memory cells.
