17878142. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17878142 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The patent application describes a semiconductor device that includes a substrate, a semiconductor chip, and bonding wires. The device also includes upper bonding pads on the substrate, each consisting of a first conductive pattern, a second conductive pattern, and a bonding layer. The first conductive pattern has a narrower width at the top surface compared to the bottom surface. The upper protection layer covers the sidewalls of the second conductive pattern.
- The semiconductor device includes a substrate with an upper protection layer and multiple upper bonding pads.
- A semiconductor chip is mounted on the substrate, and bonding wires connect the chip to the upper bonding pads.
- Each upper bonding pad consists of a first conductive pattern, a second conductive pattern, and a bonding layer.
- The second conductive pattern covers the top surface and sidewall of the first conductive pattern and contains the same metal element.
- The width of the first conductive pattern is narrower at the top surface than at the bottom surface.
- The upper protection layer covers the sidewalls of the second conductive pattern.
Potential Applications
- Semiconductor manufacturing industry
- Electronics industry
- Integrated circuit design and production
Problems Solved
- Improved bonding pad structure for semiconductor devices
- Enhanced protection of bonding pads from external factors
- More efficient and reliable electrical connections
Benefits
- Increased durability and reliability of semiconductor devices
- Improved electrical performance and signal transmission
- Enhanced protection against environmental factors
Original Abstract Submitted
A semiconductor device includes a substrate that includes an upper protection layer and a plurality of upper bonding pads, a semiconductor chip on the substrate, and a plurality of bonding wires connected to the semiconductor chip and the upper bonding pads. Each of the upper bonding pads includes a first conductive pattern, a second conductive pattern that covers a top surface and a sidewall of the first conductive pattern and includes a metal element the same as a metal element of the first conductive pattern, and a bonding layer on the second conductive pattern. A width at the top surface of the first conductive pattern is less than a width at a bottom surface of the first conductive pattern. The upper protection layer covers sidewalls of the second conductive pattern.
