17877592. MEMORY ROW-HAMMER MITIGATION simplified abstract (Micron Technology, Inc.)

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MEMORY ROW-HAMMER MITIGATION

Organization Name

Micron Technology, Inc.

Inventor(s)

Bryan David Kerstetter of Kuna ID (US)

Alan J. Wilson of Boise ID (US)

Donald Martin Morgan of Meridian ID (US)

MEMORY ROW-HAMMER MITIGATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17877592 titled 'MEMORY ROW-HAMMER MITIGATION

Simplified Explanation

Methods, systems, and devices for memory row-hammer mitigation are described in this patent application. The memory device operates based on a continuous scheme across power cycles. It determines whether to access a specific region based on the value of a counter. If the counter value does not satisfy a threshold value, the memory device accesses the region. Conversely, if the counter value satisfies the threshold value, the memory device also accesses the region. When transitioning power states, the counter value is stored in a non-volatile memory, allowing it to be accessed when transitioning back to the original power state. This ensures that the counter value is maintained across power cycles.

  • The memory device uses a counter to determine whether to access a specific region.
  • The counter value is compared to a threshold value to make the access decision.
  • The counter value is stored in non-volatile memory during power state transitions.
  • The stored counter value is retrieved when transitioning back to the original power state.

Potential applications of this technology:

  • Memory devices in computers, servers, and other electronic devices that require row-hammer mitigation.
  • Systems that rely on memory integrity and need protection against row-hammer attacks.

Problems solved by this technology:

  • Row-hammer attacks, where repeated access to a specific memory row can cause bit flips in adjacent rows, are mitigated.
  • Memory integrity is maintained by preventing unauthorized access to specific memory regions.

Benefits of this technology:

  • Enhanced security by preventing row-hammer attacks.
  • Improved memory reliability and integrity.
  • Continuous operation across power cycles without loss of counter value.


Original Abstract Submitted

Methods, systems, and devices for memory row-hammer mitigation are described. A memory device may operate based on a scheme that is continuous across power cycles. For example, the memory device may access a region if a value of a counter does not satisfy a threshold value and may access the region if a value of the counter satisfies the threshold value. Upon transitioning power states, the value of the counter may be stored to a non-volatile memory such that it may be accessed when transitioning back to the original power state (e.g., an “ON” state). Accordingly, the value of the counter may be maintained across power cycles.

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