17874100. Non-Volatile Memory Power Cycle Protection Mechanism simplified abstract (Apple Inc.)

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Non-Volatile Memory Power Cycle Protection Mechanism

Organization Name

Apple Inc.

Inventor(s)

John J. Sullivan of Sunnyvale CA (US)

James M. Hollabaugh of San Jose CA (US)

Jason W. Brinsfield of San Francisco CA (US)

Calvin M. Ryan of Berkeley CA (US)

Andreas Adler of Schlierbach (DE)

Non-Volatile Memory Power Cycle Protection Mechanism - A simplified explanation of the abstract

This abstract first appeared for US patent application 17874100 titled 'Non-Volatile Memory Power Cycle Protection Mechanism

Simplified Explanation

The abstract describes techniques for protecting non-volatile memory (NVM) from power cycle interruptions during memory operations. A power management integrated circuit (PMIC) is coupled to a memory circuit with NVM to implement these techniques.

  • The PMIC delays the initiation of the power reset cycle when it detects that the NVM is active, preventing corruption of the NVM by the power reset cycle.
  • The PMIC detects the activity level of the NVM based on an activity output signal, which indicates whether the NVM is active (e.g., programming or erasing) or inactive.

Potential applications of this technology:

  • Embedded systems: This technology can be used in embedded systems that rely on non-volatile memory for storing critical data. It ensures that power cycle interruptions do not corrupt the memory during important operations.
  • Data storage devices: NVM-based data storage devices, such as solid-state drives (SSDs), can benefit from this technology to protect data integrity during power cycles.

Problems solved by this technology:

  • Power cycle interruptions: Power cycles can cause data corruption in NVM if not handled properly. This technology solves the problem by delaying the power reset cycle when the NVM is active, preventing corruption.
  • Data integrity: By protecting the NVM from power cycle interruptions, this technology ensures the integrity of the stored data, preventing data loss or corruption.

Benefits of this technology:

  • Data reliability: The technology ensures that data stored in NVM remains reliable even during power cycle interruptions, providing peace of mind to users.
  • Extended NVM lifespan: By preventing data corruption, this technology can help extend the lifespan of NVM-based memory devices, reducing the need for frequent replacements.


Original Abstract Submitted

Techniques for protecting non-volatile memory (NVM) from power cycle interruptions during memory operations are disclosed. A power management integrated circuit (PMIC) coupled to a memory circuit with NVM implements the various techniques disclosed. When a power reset signal is asserted to a PMIC, the PMIC may delay initiation of the power reset cycle when it detects that the NVM coupled to the PMIC is active to prevent corruption of the NVM by the power reset cycle. The PMIC may detect the activity level of the NVM based on an activity output signal that indicates whether the NVM is active (e.g., programming or erasing) or inactive.

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