17862469. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

SEMICONDUCTOR PACKAGE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

JEONGHWAN Lee of HWASEONG-SI (KR)

ILHO Kim of YONGIN-SI (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17862469 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The abstract describes a semiconductor package that includes multiple semiconductor chips connected to an interposer and surrounded by molding layers.

• The semiconductor package includes a package substrate, an interposer, and molding layers.
• A first semiconductor chip is placed on a lower molding layer, with a chip connection terminal connecting it to the package substrate.
• A second semiconductor chip is also placed on the lower molding layer, at the outer side of the first semiconductor chip.
• Interposer connection terminals are used to connect both semiconductor chips to the interposer.
• An upper molding layer surrounds the first and second semiconductor chips.

Potential applications of this technology:

• This semiconductor package design can be used in various electronic devices, such as smartphones, tablets, and computers.
• It can be applied in automotive electronics, medical devices, and industrial equipment.

Problems solved by this technology:

• The design allows for efficient integration of multiple semiconductor chips in a compact package.
• It provides a reliable connection between the chips and the interposer, ensuring stable performance.

Benefits of this technology:

• The compact design saves space and allows for smaller and thinner electronic devices.
• The reliable chip-to-interposer connection enhances the overall performance and reliability of the semiconductor package.

Original Abstract Submitted

A semiconductor package includes a package substrate, an interposer on the package substrate, a lower molding layer on the package substrate and surrounding the interposer, a first semiconductor chip on the lower molding layer, a chip connection terminal between the first semiconductor chip and the package substrate and surrounded by the lower molding layer, a second semiconductor chip on the lower molding layer and at an outer side of the first semiconductor chip, interposer connection terminals that connect the first and second semiconductor chips to the interposer, and an upper molding layer on the lower molding layer and surrounding the first and second semiconductor chips.