17834992. SEMICONDUCTOR DEVICES simplified abstract (Samsung Electronics Co., Ltd.)
Contents
SEMICONDUCTOR DEVICES
Organization Name
Inventor(s)
Kyungsoo Kim of Hwaseong-si (KR)
SEMICONDUCTOR DEVICES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17834992 titled 'SEMICONDUCTOR DEVICES
Simplified Explanation
The abstract describes a semiconductor device that includes various components such as active regions, gate electrodes, source/drain regions, buried interconnection lines, and contact plugs.
- The device has a substrate with active regions and gate electrodes intersecting them.
- Source/drain regions are located in recessed areas of the active regions.
- Buried interconnection lines are present in the substrate.
- Two lower contact plugs connect the source/drain regions and gate electrodes to the buried interconnection lines.
- Upper contact plugs are connected to the source/drain regions and gate electrodes.
- The upper surfaces of the lower contact plugs are positioned lower than the upper surfaces of the gate electrodes.
Potential applications of this technology:
- Integrated circuits
- Microprocessors
- Memory devices
- Power devices
Problems solved by this technology:
- Efficient connection between different components of the semiconductor device
- Reduction of signal loss and interference
- Improved performance and reliability of the device
Benefits of this technology:
- Enhanced functionality and performance of semiconductor devices
- Increased integration density
- Improved signal transmission and connectivity
- Enhanced reliability and durability of the device
Original Abstract Submitted
A semiconductor device, includes: a substrate including active regions extending in a first direction; gate electrodes extending in a second direction, intersecting the active regions; source/drain regions disposed in regions in which the active regions are recessed; buried interconnection lines disposed in the substrate; a first lower contact plug penetrating through a portion of the substrate, and connecting at least one of the source/drain regions and at least one of the buried interconnection lines; a second lower contact plug penetrating through a portion of the substrate, and connecting at least one of the gate electrodes and at least one of the buried interconnection lines; and upper contact plugs connected to a portion of the source/drain regions and a portion of the gate electrodes, wherein upper surfaces of the first and second lower contact plugs are disposed on a level lower than a level of upper surfaces of the gate electrodes.
