17831332. PRE-DECODER CIRCUITY simplified abstract (Micron Technology, Inc.)

PRE-DECODER CIRCUITY

Organization Name

Micron Technology, Inc.

Inventor(s)

Jin Seung Son of McKinney TX (US)

Mingdong Cui of Folsom CA (US)

PRE-DECODER CIRCUITY - A simplified explanation of the abstract

This abstract first appeared for US patent application 17831332 titled 'PRE-DECODER CIRCUITY

Simplified Explanation

The patent application describes a technology for pre-decoder circuitry used in memory arrays. The circuitry includes a decoder and pre-decoder circuitry that provide bias conditions to select memory cells.

• The pre-decoder circuitry includes two types of transistors and provides different voltages to the gates of these transistors based on the memory cell configuration.
• For a positive memory cell configuration, the first gate receives a positive voltage and the second gate receives a negative voltage.
• For a negative memory cell configuration, the first gate receives zero volts and the second gate receives a negative voltage.
• The pre-decoder circuitry consists of two parts: first pre-decoder circuitry that provides the positive voltage and zero volts, and second pre-decoder circuitry that provides the negative voltage.

Potential applications of this technology:

• Memory arrays in electronic devices such as computers, smartphones, and tablets.
• Data storage systems in servers and data centers.
• High-performance computing systems that require efficient memory access.

Problems solved by this technology:

• Efficient selection of memory cells in a memory array.
• Simplification of the pre-decoder circuitry design.
• Improved performance and reliability of memory arrays.

Benefits of this technology:

• Faster and more accurate selection of memory cells.
• Reduced power consumption in memory arrays.
• Improved overall performance and efficiency of electronic devices.

Original Abstract Submitted

The disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the array and comprising a first and second n-type transistor having a first and second gate, respectively, and pre-decoder circuitry to provide a bias condition for the first and second gate to provide a selection signal to one of the cells. The bias condition comprises a positive voltage for the first gate and a negative voltage for the second gate for a positive memory cell configuration, and zero volts for the first gate and the negative voltage for the second gate for a negative memory cell configuration. The pre-decoder circuitry comprises first pre-decoder circuitry to provide the positive voltage for the first gate and the zero volts for the second gate and second pre-decoder circuitry to provide the negative voltage for the second gate.