17827302. PERFORMANCE AWARE PARTIAL CACHE COLLAPSE simplified abstract (QUALCOMM Incorporated)
Contents
PERFORMANCE AWARE PARTIAL CACHE COLLAPSE
Organization Name
Inventor(s)
Hithesh Hassan Lepaksha of Hyderabad (IN)
Sharath Kumar Nagilla of Hyderabad (IN)
Darshan Kumar Nandanwar of Bangalore (IN)
Nirav Narendra Desai of Hyderabad (IN)
Venkata Biswanath Devarasetty of Hyderabad (IN)
PERFORMANCE AWARE PARTIAL CACHE COLLAPSE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17827302 titled 'PERFORMANCE AWARE PARTIAL CACHE COLLAPSE
Simplified Explanation
The present disclosure relates to systems and methods for improving the performance of a partial cache collapse by a processing device. The method includes counting the number of cache lines that meet an eviction criteria in each cache way of a group of cache ways. Based on this count, at least one cache way is selected from the group for collapse. The partial cache collapse procedure is then performed based on the selected cache way(s).
- The method counts the number of cache lines that satisfy an eviction criteria in each cache way.
- At least one cache way is selected from a group of cache ways for collapse based on the count.
- The partial cache collapse procedure is performed based on the selected cache way(s).
Potential applications of this technology:
- Improving the performance of processing devices that utilize cache memory.
- Enhancing the efficiency of cache management in computer systems.
- Optimizing the utilization of cache resources in high-performance computing.
Problems solved by this technology:
- Inefficient cache management can lead to reduced performance and increased latency in processing devices.
- Inadequate utilization of cache resources can limit the overall performance of a computer system.
- Ineffective cache eviction policies can result in unnecessary cache evictions and reduced cache hit rates.
Benefits of this technology:
- Improved performance and reduced latency in processing devices.
- Enhanced efficiency and utilization of cache resources.
- Increased cache hit rates and overall system performance.
Original Abstract Submitted
Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting a number of cache lines that satisfy an eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways; selecting at least one cache way from the group for collapse, based on its corresponding number of cache lines that satisfy the eviction criteria; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.
