17826505. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Jihwang Kim of CHEONAN-SI (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17826505 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The semiconductor package described in this patent application includes multiple semiconductor chips and a cooling system. Here are the key points:
- The package consists of a first semiconductor chip and a second semiconductor chip stacked on top of each other.
- A chip connection terminal is used to establish electrical connections between the two chips.
- An underfill layer is placed between the chips and around the chip connection terminal for support and insulation.
- The package features a vertical porous structure that fills the spaces of vertical cooling channels passing through both chips and the underfill layer.
- The vertical porous structure contains cooling holes that allow a cooling fluid to flow through the vertical cooling channels.
Potential applications of this technology:
- This semiconductor package can be used in various electronic devices, such as computers, smartphones, and gaming consoles.
- It can be particularly beneficial in high-performance devices that generate a significant amount of heat, as the cooling system helps dissipate heat efficiently.
Problems solved by this technology:
- The vertical porous structure and cooling system address the issue of heat buildup in semiconductor chips, which can lead to performance degradation and even failure.
- By providing a reliable cooling solution, this technology helps maintain optimal operating temperatures for the chips, improving their overall performance and lifespan.
Benefits of this technology:
- The cooling system ensures efficient heat dissipation, preventing overheating and potential damage to the semiconductor chips.
- By maintaining lower operating temperatures, the technology can enhance the performance and reliability of electronic devices.
- The vertical porous structure and cooling channels offer a compact and effective cooling solution, allowing for more efficient use of space within the semiconductor package.
Original Abstract Submitted
A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, a chip connection terminal configured to electrically connect the first semiconductor chip to the second semiconductor chip, an underfill layer disposed between the first semiconductor chip and the second semiconductor chip and surrounding the chip connection terminal, a vertical porous structure filling spaces of a plurality of vertical cooling channels passing through the first semiconductor chip, the second semiconductor chip, and the underfill layer in a vertical direction, and having a plurality of cooling holes, and a cooling fluid provided to the plurality of cooling holes of the vertical porous structure to flow inside the plurality of vertical cooling channels.
