17823909. MEMORY WITH SWITCHABLE CHANNELS simplified abstract (Micron Technology, Inc.)
Contents
MEMORY WITH SWITCHABLE CHANNELS
Organization Name
Inventor(s)
Sundararajan Sankaranarayanan of Fremont CA (US)
Chulbum Kim of San Jose CA (US)
Xiangyu Tang of San Jose CA (US)
MEMORY WITH SWITCHABLE CHANNELS - A simplified explanation of the abstract
This abstract first appeared for US patent application 17823909 titled 'MEMORY WITH SWITCHABLE CHANNELS
Simplified Explanation
The patent application discloses memory with switchable channels, where a system comprises a controller, memory dies, and a switch matrix for dynamically configurable connections between the controller and memory dies.
- The system includes a controller, multiple memory dies, and a switch matrix.
- The switch matrix connects the controller to the memory dies through controller-side channels and memory-side channels.
- The switch matrix can selectively couple controller-side channels to memory-side channels for configurable connections.
- This allows for flexible and dynamic configurations between the controller and memory dies.
Potential Applications
- Data centers
- High-performance computing
- Artificial intelligence and machine learning systems
Problems Solved
- Efficient data transfer between controller and memory dies
- Flexibility in configuring memory connections
- Improved system performance and scalability
Benefits
- Increased data processing speed
- Enhanced system flexibility and adaptability
- Improved overall system performance and efficiency
Original Abstract Submitted
Memory with switchable channels is disclosed herein. In one embodiment, a system comprises a controller, a plurality of memory dies, and a switch matrix. The switch matrix is coupled to the controller via two or more controller-side channels, and to the plurality of memory dies via a set of memory-side channels. The switch matrix is configured to selectively couple each controller-side channel of the two or more controller-side channels to each memory-side channel of the set of memory-side channels to provide dynamically configurable connections between the controller and one or more memory dies of the plurality of memory dies.
