17823407. Adaptive Memory Registers simplified abstract (Micron Technology, Inc.)
Contents
Adaptive Memory Registers
Organization Name
Inventor(s)
John Christopher Sancon of Boise ID (US)
Kang-Yong Kim of Boise ID (US)
Adaptive Memory Registers - A simplified explanation of the abstract
This abstract first appeared for US patent application 17823407 titled 'Adaptive Memory Registers
Simplified Explanation
The patent application describes adaptive memory registers for a memory system that supports a nondeterministic protocol. The apparatus includes logic for writing values to memory registers associated with memory blocks to indicate if they have been refreshed within a refresh interval. Other logic can read the registers to determine if a block has been refreshed. The device also includes logic to access data indicating the most recently or next to be refreshed row address, and write values representing the address to another register. This register can be read to determine if a wordline potentially affected by an activation-based disturb event is near to being refreshed. These techniques aim to reduce the number of refresh operations, saving power and reducing costs.
- Memory system with adaptive memory registers
- Registers indicate if memory blocks have been refreshed within a refresh interval
- Logic to access and write row addresses for refresh
- Helps reduce the number of refresh operations, saving power and reducing costs
Potential Applications
- Memory systems in mobile devices - Data centers - Internet of Things (IoT) devices
Problems Solved
- Power consumption in memory systems - Cost of frequent refresh operations - Management of power-delivery networks
Benefits
- Reduced power consumption - Cost savings - Improved efficiency in memory systems
Original Abstract Submitted
Described apparatuses and methods relate to adaptive memory registers for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a device includes logic that can write values to memory registers associated with memory blocks of a memory array. The values indicate whether an associated memory block has been refreshed within a refresh interval. Other logic can read the registers to determine whether a block has been refreshed. The device also includes logic that can access data indicating a row address that was most recently, or is next to be, refreshed and write values representing the address to another register. The register can be read by other logic to determine whether a wordline potentially affected by an activation-based disturb event is near to being refreshed. These techniques can reduce the number of refresh operations performed, saving power and reducing costs.
