17823323. MEMORY SIDE CACHE REQUEST HANDLING simplified abstract (Micron Technology, Inc.)
Contents
MEMORY SIDE CACHE REQUEST HANDLING
Organization Name
Inventor(s)
Dean E. Walker of Allen TX (US)
Tony M. Brewer of Plano TX (US)
MEMORY SIDE CACHE REQUEST HANDLING - A simplified explanation of the abstract
This abstract first appeared for US patent application 17823323 titled 'MEMORY SIDE CACHE REQUEST HANDLING
Simplified Explanation
- Explanation:**
- System and techniques for memory side cache request handling are described. - Memory request is received and cache set is determined. - Cache set has multiple ways, each corresponding to a cache line. - If a way is not ready for the memory request, the request is stored in a queue. - Entries from the queues are dequeued in a defined order to process the next memory request. - Priority is given to present way requests over external and internal requests.
- Potential Applications:**
- Computer systems - Data centers - Cloud computing
- Problems Solved:**
- Efficient handling of memory requests - Optimization of cache usage - Prioritization of memory requests
- Benefits:**
- Improved performance - Reduced latency - Enhanced cache utilization
Original Abstract Submitted
System and techniques for memory side cache request handling are described herein. When a memory request is received, a cache set for the memory request is determined. Here, the cache set has multiple ways and each way corresponds to a cache line. It can be detected that a way of the multiple ways is not ready for the memory request. In this case, a representation of the memory request is stored in a queue of multiple queues based on an interface upon which the memory request was received and the present ways of the cache set. Entries from the multiple queues can be dequeued in a defined order to determine a next memory request to process. The defined order gives priority to memory requests for a present way and then for external over internal requests.
