17823314. HOST-PREFERRED MEMORY OPERATION simplified abstract (Micron Technology, Inc.)

HOST-PREFERRED MEMORY OPERATION

Organization Name

Micron Technology, Inc.

Inventor(s)

Tony M. Brewer of Plano TX (US)

Dean E. Walker of Allen TX (US)

HOST-PREFERRED MEMORY OPERATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17823314 titled 'HOST-PREFERRED MEMORY OPERATION

Simplified Explanation

The abstract describes a system and techniques for host-preferred memory operation, where memory operations from a host and accelerator hardware are managed efficiently in a memory-side cache.

• Memory operations are received from a host and accelerator hardware.
• The operations are determined to correspond to a cache set based on their addresses.
• The operations are enqueued in separate queues within the cache set.
• The operations are executed as they are dequeued.

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1. 1. 1. Potential Applications

• This technology can be applied in high-performance computing systems.
• It can be used in data centers to optimize memory operations.
• It can improve the efficiency of memory management in embedded systems.

1. 1. 1. Problems Solved

• Efficient management of memory operations from hosts and accelerator hardware.
• Optimization of memory access in cache sets.
• Improved performance and reduced latency in memory operations.

1. 1. 1. Benefits

• Enhanced performance in memory operations.
• Reduced latency in accessing memory.
• Efficient utilization of memory-side cache in memory devices.

Original Abstract Submitted

System and techniques for host-preferred memory operation are described herein. At a memory-side cache of a memory device that includes accelerator hardware, a first memory operation can be received from a host. A determination that the first memory operation corresponds to a cache set based on an address of the first memory operation is made. A second memory operation can be received from the accelerator hardware. Another determination can be made that the second memory operation corresponds to the cache set. Here, the first memory operation can be enqueued in a host queue of the cache set and the second memory operation can be enqueued in an internal request queue of the cache set. The first memory operation and the second memory operation can be executed as each is dequeued.