17802053. IMPROVED ECC CONFIGURATION IN MEMORIES simplified abstract (Micron Technology, Inc.)
Contents
IMPROVED ECC CONFIGURATION IN MEMORIES
Organization Name
Inventor(s)
Graziano Mirichigni of Vimercate (IT)
Christophe Laurent of Agrate Brianza (IT)
Riccardo Muzzetto of Arcore (IT)
IMPROVED ECC CONFIGURATION IN MEMORIES - A simplified explanation of the abstract
This abstract first appeared for US patent application 17802053 titled 'IMPROVED ECC CONFIGURATION IN MEMORIES
The present disclosure describes a method for operating an array of memory cells, involving storing user data and associated parity data in different cells of the array. Based on the stored parity data, an Error Correction Code (ECC) correction capability and/or ECC granularity are selected for performing ECC operations. This selection is determined by updating a first register with values indicating the required ECC correction capability and/or granularity based on the current status of the memory cells. An ECC switch command is executed based on the updated values, which vary the previously selected ECC correction capability and/or granularity. A second register is then updated with the varied ECC correction capability and/or granularity.
- Storing user data and parity data in memory cells of an array
- Selecting ECC correction capability and granularity based on stored parity data
- Updating registers with required ECC parameters based on memory cell status
- Executing ECC switch command to vary ECC parameters
- Updating second register with varied ECC parameters
Potential Applications: - Data storage systems - Error correction in memory devices - Data integrity in electronic systems
Problems Solved: - Efficient error correction in memory arrays - Adaptive ECC capabilities based on data status
Benefits: - Improved data reliability - Enhanced error correction efficiency - Adaptive ECC operations based on real-time data status
Commercial Applications: Title: Adaptive Error Correction Method for Memory Arrays This technology can be used in: - Solid-state drives - Servers and data centers - Embedded systems
Prior Art: Prior research on adaptive ECC methods in memory systems can provide insights into similar approaches to error correction.
Frequently Updated Research: Stay updated on advancements in ECC algorithms and memory system technologies to enhance error correction capabilities.
Questions about Adaptive Error Correction Method for Memory Arrays:
1. How does this method improve data reliability in memory systems? 2. What are the potential challenges in implementing adaptive ECC capabilities in memory arrays?
Original Abstract Submitted
The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction capability and/or a required ECC granularity to be applied to said memory cells, and based on the updated values of the first register, executing an ECC switch command, wherein the ECC switch command is such as to vary a previously selected ECC correction capability and/or a previously selected ECC granularity, the method further comprising: updating a second register according to the varied ECC correction capability and/or ECC granularity, said second register comprising values indicating the selected ECC correction capability and the selected ECC granularity applied to the memory cells based on the current status thereof. Related apparatuses and systems are also herein disclosed.
