17789505. ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE AND DISPLAY PANEL simplified abstract (BOE Technology Group Co., Ltd.)
Contents
- 1 ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE AND DISPLAY PANEL
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE AND DISPLAY PANEL - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Potential Applications
- 1.6 Problems Solved
- 1.7 Benefits
- 1.8 Potential Commercial Applications
- 1.9 Possible Prior Art
- 1.10 Original Abstract Submitted
ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE AND DISPLAY PANEL
Organization Name
BOE Technology Group Co., Ltd.
Inventor(s)
ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE AND DISPLAY PANEL - A simplified explanation of the abstract
This abstract first appeared for US patent application 17789505 titled 'ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE AND DISPLAY PANEL
Simplified Explanation
The array substrate described in the patent application includes gate lines, data lines, thin film transistors, conductive layers, insulating layers, wiring patterns, interconnection patterns, via holes, and pixel units.
- The array substrate consists of a base with gate lines and data lines.
- Each pixel unit contains a thin film transistor.
- The first conductive layer has a wiring pattern, while the second conductive layer has an interconnection pattern.
- The wiring pattern and interconnection pattern overlap on the base.
- Data lines are part of the first conductive layer and have auxiliary lines formed by the interconnection pattern in the second conductive layer.
- The wiring pattern includes the data lines, and either the data line or the interconnection pattern is connected to the thin film transistor's source.
Potential Applications
The technology described in this patent application could be used in the manufacturing of high-resolution displays, such as LCD screens, OLED displays, and touchscreens.
Problems Solved
This technology solves the problem of efficiently connecting data lines and interconnection patterns in array substrates, improving the overall performance and reliability of the display.
Benefits
The benefits of this technology include increased display resolution, improved image quality, reduced power consumption, and enhanced durability of the array substrate.
Potential Commercial Applications
A potential commercial application of this technology could be in the production of smartphones, tablets, computer monitors, and other electronic devices with high-quality displays.
Possible Prior Art
One possible prior art for this technology could be the use of similar conductive layers and wiring patterns in the manufacturing of array substrates for electronic displays.
Unanswered Questions
How does this technology compare to existing array substrates in terms of cost-effectiveness?
This article does not provide information on the cost-effectiveness of the technology compared to existing array substrates.
What impact does this technology have on the overall performance of the display?
The article does not address the specific impact of this technology on the overall performance of the display.
Original Abstract Submitted
An array substrate includes: a base; gate lines and data lines on the base; multiple pixel units each including a thin film transistor; first and second conductive layers with a first insulating layer therebetween. The first conductive layer includes a first wiring pattern, the second conductive layer includes a first interconnection pattern, orthographic projections of the first wiring pattern and the first interconnection pattern on the base are at least partially overlapped. The first wiring pattern is connected with the first interconnection pattern through a via hole. Each of part of data lines is located in the first conductive layer and has an auxiliary line formed by the first interconnection pattern in the second conductive layer. The first wiring pattern includes the data lines; at least one of the data line and the first interconnection pattern is connected to a source of the thin film transistor.
