17782979. DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS simplified abstract (CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.)

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DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS

Organization Name

CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor(s)

Hong Yi of Beijing (CN)

Tiaomei Zhang of Beijing (CN)

Haigang Qing of Beijing (CN)

DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS - A simplified explanation of the abstract

This abstract first appeared for US patent application 17782979 titled 'DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS

Simplified Explanation

The display substrate described in the patent application includes various components such as signal lines, planarization layers, and via holes, all arranged in a specific configuration to improve display performance.

  • The display substrate includes first and second signal lines located in the periphery area, with the first signal line positioned between the display area and the second signal line.
  • A first spacing region is provided between the projection of the first signal line onto the base of the display substrate and the projection of the second signal line onto the base.
  • The first planarization layer includes a first planarization portion located at the periphery area, while the second planarization layer includes a first via hole that overlaps with the first spacing region at a first overlap region.
  • The projection of the first planarization portion onto the base also overlaps with the first overlap region at a second overlap region.

Potential Applications

This technology could be applied in the manufacturing of high-resolution displays for electronic devices such as smartphones, tablets, and televisions.

Problems Solved

This innovation helps to reduce signal interference and improve the overall display quality by carefully designing the layout of signal lines and planarization layers on the display substrate.

Benefits

- Enhanced display performance - Reduced signal interference - Improved image quality

Potential Commercial Applications

The technology could be utilized by display manufacturers looking to enhance the quality and resolution of their products, catering to the growing demand for high-definition displays in consumer electronics.

Possible Prior Art

Prior art related to display substrates and signal line layouts in display manufacturing processes may exist, but specific examples are not provided in the patent application.

Unanswered Questions

How does this technology compare to existing display substrate designs in terms of signal quality and display performance?

The patent application does not directly address a comparison with existing display substrate designs, leaving room for further analysis and research in this area.

What specific electronic devices or industries could benefit the most from implementing this display substrate technology?

While the potential applications are mentioned broadly, a more detailed exploration of the target markets and industries that could benefit the most from this technology is not provided in the patent application.


Original Abstract Submitted

Display substrate, manufacturing method thereof and display apparatus are provided. The display substrate includes display and periphery areas, and further includes: first and second signal lines, first and second planarization layers, where each of first and second signal lines is located at periphery area, and includes portion extending in first direction; at least part of first signal line is located between display area and second signal line, first spacing region is provided between projection of first signal line onto base of display substrate and projection of second signal line onto base; first planarization portion including first planarization portion located at periphery area; second planarization layer including first via hole, projection of which onto base overlaps with first spacing region at first overlap region; and projection of first planarization portion onto base overlaps with first overlap region at second overlap region.