17772761. DISPLAYING BASE PLATE AND MANUFACTURING METHOD THEREOF, AND DISPLAYING DEVICE simplified abstract (BOE TECHNOLOGY GROUP CO., LTD.)

DISPLAYING BASE PLATE AND MANUFACTURING METHOD THEREOF, AND DISPLAYING DEVICE

Organization Name

BOE TECHNOLOGY GROUP CO., LTD.

Inventor(s)

Fuqiang Li of Beijing (CN)

Zhen Zhang of Beijing (CN)

Zhenyu Zhang of Beijing (CN)

Lizhong Wang of Beijing (CN)

Ce Ning of Beijing (CN)

Yunping Di of Beijing (CN)

Zheng Fang of Beijing (CN)

Jiahui Han of Beijing (CN)

Chenyang Zhang of Beijing (CN)

Yawei Wang of Beijing (CN)

Chengfu Xu of Beijing (CN)

DISPLAYING BASE PLATE AND MANUFACTURING METHOD THEREOF, AND DISPLAYING DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17772761 titled 'DISPLAYING BASE PLATE AND MANUFACTURING METHOD THEREOF, AND DISPLAYING DEVICE

Simplified Explanation

The thin film transistor described in the patent application includes an active layer, a first insulating layer, and a gate layer stacked together. The active layer consists of a source contact area, a drain contact area, and a channel area connecting the two contact areas. The channel area is further divided into a first channel area, a first resistance area, and a second channel area in a sequential manner. The gate layer includes a first gate and a second gate, each covering a specific channel area when projected onto the plane where the active layer is located.

• Active layer, first insulating layer, and gate layer stacked in the thin film transistor
• Channel area divided into first channel area, first resistance area, and second channel area
• First gate and second gate in the gate layer covering specific channel areas when projected onto the active layer plane

Potential Applications

The technology described in the patent application could be used in the manufacturing of high-resolution displays, touchscreens, and other electronic devices requiring thin film transistors.

Problems Solved

This technology solves the problem of improving the performance and efficiency of thin film transistors by optimizing the layout and design of the active layer and gate layer.

Benefits

The benefits of this technology include increased display resolution, enhanced touchscreen sensitivity, and improved overall performance of electronic devices utilizing thin film transistors.

Potential Commercial Applications

The potential commercial applications of this technology include the production of smartphones, tablets, laptops, and other electronic devices with high-quality displays and efficient thin film transistors.

Possible Prior Art

One possible prior art related to this technology is the development of thin film transistors with multiple gate layers for improved performance and functionality in electronic devices.

How does this technology compare to traditional thin film transistors in terms of performance and efficiency?

The patent application does not provide a direct comparison between this technology and traditional thin film transistors in terms of performance and efficiency. Further research or testing may be needed to evaluate the differences.

What are the potential challenges in implementing this technology on a large scale for commercial production?

The patent application does not address the potential challenges in implementing this technology on a large scale for commercial production. Factors such as cost, scalability, and compatibility with existing manufacturing processes could be important considerations.

Original Abstract Submitted

Disclosed are a thin film transistor and a manufacturing method therefor, a displaying base plate and a displaying apparatus. The thin film transistor includes an active layer, a first insulating layer and a gate layer which are disposed in stack, wherein the active layer includes a source contact area, a drain contact area, and a channel area connecting the source contact area and the drain contact area; the channel area includes a first channel area, a first resistance area and a second channel area sequentially disposed in a first direction; the gate layer includes a first gate and a second gate which are separately disposed; an orthographic projection of the first gate on a plane where the active layer is located covers the first channel area; and an orthographic projection of the second gate on a plane where the active layer is located covers the second channel area.