17725729. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17725729 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The patent application describes a semiconductor package that includes a substrate with different regions, a passive element, a semiconductor chip, and a sealing portion. The peripheral region of the substrate has four sub-regions, and the upper surface of at least one of these sub-regions has a greater roughness compared to the remaining region.
- The semiconductor package includes a substrate with different regions: passive element region, peripheral region, and remaining region.
- A first passive element is located on the upper surface of the passive element region.
- A first semiconductor chip is located on the upper surface of the remaining region.
- The substrate, first passive element, and first semiconductor chip are covered by a sealing portion.
- The peripheral region of the substrate consists of four sub-regions: first, second, third, and fourth sub-regions.
- The upper surface of at least one of the first to fourth sub-regions has a greater roughness compared to the upper surface of the remaining region.
Potential applications of this technology:
- Semiconductor packaging industry
- Electronics manufacturing
Problems solved by this technology:
- Provides a semiconductor package with improved performance and reliability
- Helps to reduce the risk of damage or failure in the peripheral region of the substrate
Benefits of this technology:
- Enhanced functionality and durability of semiconductor packages
- Improved overall performance and reliability of electronic devices.
Original Abstract Submitted
A semiconductor package includes a substrate having a passive element region, a peripheral region adjacent to the passive element region, and a remaining region, a first passive element on an upper surface of the passive element region, a first semiconductor chip on an upper surface of the remaining region, and a sealing portion covering the substrate, the first passive element, and the first semiconductor chip, wherein the peripheral region includes a first sub-region on a first side of the first passive element, a second sub-region on a second side opposite the first side, a third sub-region on a third side of the first passive element, and a fourth sub-region on a fourth side opposite the third side, and wherein a roughness of an upper surface of at least one of the first to fourth sub-regions is greater than a roughness of the upper surface of the remaining region.
