17699931. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

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SEMICONDUCTOR PACKAGE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

Hwan-Wook Jung of Gwangmyeong-si (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17699931 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The patent application describes a semiconductor package that includes multiple chip stacks and a spacer. The first chip stack is arranged in an offset stack structure and exposes a connection region on each chip's top surface. The second chip stack is placed horizontally apart from the first chip stack and includes additional semiconductor chips. Each first semiconductor chip has a chip pad and a wire connecting it to the substrate. The uppermost first semiconductor chip is spaced apart from the lowermost third semiconductor chip.

  • The semiconductor package includes multiple chip stacks and a spacer.
  • The first chip stack is arranged in an offset stack structure and exposes a connection region on each chip's top surface.
  • The second chip stack is placed horizontally apart from the first chip stack.
  • Each first semiconductor chip has a chip pad and a wire connecting it to the substrate.
  • The uppermost first semiconductor chip is spaced apart from the lowermost third semiconductor chip.

Potential Applications

  • This semiconductor package can be used in various electronic devices such as smartphones, tablets, and computers.
  • It can be applied in high-performance computing systems, where multiple chips need to be stacked and connected efficiently.

Problems Solved

  • The offset stack structure and spacer allow for a compact and efficient arrangement of multiple semiconductor chips.
  • The exposed connection regions on each chip's top surface simplify the interconnection process.
  • The horizontal spacing between the uppermost and lowermost chips prevents interference and potential damage.

Benefits

  • The semiconductor package provides a space-saving solution for stacking multiple chips.
  • The exposed connection regions make it easier to connect and integrate the chips.
  • The horizontal spacing ensures proper functioning and reduces the risk of damage.


Original Abstract Submitted

Disclosed is a semiconductor package comprising a first chip stack including on a substrate a plurality of first semiconductor chips in an offset stack structure and stacked to expose a connection region at a top surface of each of the first semiconductor chips, a second semiconductor chip on the substrate and horizontally spaced apart from the first chip stack, a spacer on the second semiconductor chip, and a second chip stack including third semiconductor chips in an offset stack structure on the first chip stack and the spacer. Each of the first semiconductor chips includes a first chip pad on the connection region and a first wire that extends between the first chip pad and the substrate. The first wire of an uppermost one of the first semiconductor chips is horizontally spaced apart from a lowermost one of the third semiconductor chips.

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